Specific Process Knowledge/Lithography/EBeamLithography/JEOLPatternPreparation

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Content and illustration by Thomas Pedersen @ DTU Nanolab unless otherwise noted.

Pattern preparation for exposure on JEOL 9500

Prior to exposure a pattern must be prepared for exposure. The original pattern must be provided in GDS format. Depending on requirements and complexity level pattern preparation will involve all or subset of the following steps.

• Alignment preparation
• Bulk and sleeve separation
• Proximity Effect Correction
• Pattern fracturing
• Field sorting
• Export for writing

Alignment preparation

Detection of alignment mark

If an exposure is first print on the substrate and there is no further EBL steps on the substrate, i.e. no EBL alignment, this step can be skipped.

If alignment is needed it is vital to consider this already at the process design and mask design level to ensure that a visible mark is produced. Alignment is done using the electron beam in either SEM mode or beam scan mode. In SEM mode the stage is moved to the expected alignment mark position and the user will manually observe the SEM image and adjust stage position to center the mark at as high magnification as required by alignment tolerance of the design. In beam scan mode the user sets up a routine that will scan the beam across the expected mark position and the Backscatter Electron Detector (BED) will detect the backscattered signal. This is done in both x- and y-directions and system will calculate the mark center based on this.

Alignment modes of JEOL 9500.

The advantage of SEM mode is that it is fairly straight forward to do. It is however also very slow as it requires constant user input to move the stage at higher and higher magnification levels until position is sufficiently determined. Due to the time it takes it is hardly realistic to do chip alignment, only global wafer alignment should be done in this way.

Automatic alignment by beam scan is significantly faster, it only takes a couple of seconds per scan. Hence this is the only realistic way of doing chip alignment. It can however be challenging to get sufficient signal on the BED for this to work if this has not already been thought into the mask and process design. Bear in mind that the electron beam is 100 kV and unless there is a relatively high difference in atomic mass between mark and substrate the signal or contrast between substrate and mark will be too low. Gold marks on Si substrates will usually work great. Deep and narrow features etched into a substrate will also work fine. Please consult with the E-beam staff or experienced colleagues when making your mark design.

Design of global marks and chip marks

As a minimum two global alignment marks must be present on the substrate for alignment. In JEOL terms these are P and Q marks. These can be used to align a full substrate design or as initial alignment of chip arrays with individual chip marks. For chip alignment either one mark (M1) or four marks (M1-M4) must be used.

Global alignment (SETWFR) has a rough scan and a fine scan setting. Initially the mark is found using the rough scan setting, which is set to scan a long distance, typically 500 µm. Once the mark is located the machine will continue with the fine scan setting which will tyipcally scan <6 µm. In order for the machine to detect the mark on the rough scan setting the cross must have sufficient width and hence the cross is typically divided into a wide part and a slim part in the center. It is recommendable to use global marks of up to 1000 µm in height and width to make them easy and fast to find.

Chip marks are only scanned after a global alignment and hence the chip mark positions are usually very well known and the chip marks can be much smaller as indicated above.