Specific Process Knowledge/Lithography/EBeamLithography/JEOLPatternPreparation: Difference between revisions
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Automatic alignment by beam scan is significantly faster, it only takes a couple of seconds per scan. Hence this is the only realistic way of doing chip alignment. It can however be challenging to get sufficient signal on the BED for this to work if this has not already been thought into the mask and process design. Bear in mind that the electron beam is 100 kV and unless there is a relatively high difference in atomic mass between mark and substrate the signal or contrast between substrate and mark will be too low. Gold marks on Si substrates will usually work great. Deep and narrow features etched into a substrate will also work fine. Please consult with the E-beam staff or experienced colleagues when making your mark design. | Automatic alignment by beam scan is significantly faster, it only takes a couple of seconds per scan. Hence this is the only realistic way of doing chip alignment. It can however be challenging to get sufficient signal on the BED for this to work if this has not already been thought into the mask and process design. Bear in mind that the electron beam is 100 kV and unless there is a relatively high difference in atomic mass between mark and substrate the signal or contrast between substrate and mark will be too low. Gold marks on Si substrates will usually work great. Deep and narrow features etched into a substrate will also work fine. Please consult with the E-beam staff or experienced colleagues when making your mark design. | ||
=== Alignment mark position and dimensions === | |||
As a minimum two global alignment marks must be present on the substrate for alignment. In JEOL terms these are P and Q marks. These can be used to align a full substrate design or as initial alignment of chip arrays with individual chip marks. For chip alignment either one mark (M1) or four marks (M1-M4) must be used. | |||
[[File:9500AlignmentMarks.png|1000px|center|frameless]] | |||