Specific Process Knowledge/Etch/DRIE-Pegasus/Pegasus-4/SiO2 Etch: Difference between revisions

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==SiO2 Etch using resist as masking material==
==SiO2 Etch using resist as masking material==
I am in the process of doing some development of a SiO2 etch. So far I have found this fairly good recipe. For now it is the standard SiO2 etch recipes but I might change the "Standard recipe" a a later time if I find a better one. You are welcome to contact me see more result. I will add them to Labadviser at a later time.
''This section is done by Berit Herstrøm @Nanolab.dtu if nothing else is stated''
/Berit Herstrøm bghe@dtu.dk (Nanolab)
I have do some development of a SiO2 etch with resist as masking material. I have found this fairly good recipe. For now it is the standard SiO2 etch recipes but I might change the "Standard recipe" a a later time if I find a better one. If you need to etch deeper than 1 micrometer then I advise you to split the etch in several runs with O2 cleans in between (3min TDESC Clean) or else it seems like the the etch rate is going down over time.


*[[/SiO2 etch with resist mask|Click here for more results on the process development on SiO2 etch with DUV resist mask]]
*[[/SiO2 etch with resist mask|Click here for more results on the process development on SiO2 etch with DUV resist mask]]

Revision as of 11:44, 27 January 2023

SiO2 Etch using resist as masking material

This section is done by Berit Herstrøm @Nanolab.dtu if nothing else is stated I have do some development of a SiO2 etch with resist as masking material. I have found this fairly good recipe. For now it is the standard SiO2 etch recipes but I might change the "Standard recipe" a a later time if I find a better one. If you need to etch deeper than 1 micrometer then I advise you to split the etch in several runs with O2 cleans in between (3min TDESC Clean) or else it seems like the the etch rate is going down over time.


SiO2 Etch using aSi as masking material

I am now starting up development of SiO2 etch using aSi as masking material.
The samples I use are:

  • 6" Si afters with oxide (2µm),
  • aSi (~300nm),
  • Neg. DUV reist (~60nm barc, ~350 nm resist)
  • Reticle: Danchip/Triple-D
  • Dose 230 J/m2

First I need to make sure that the resist work for pattering the aSi layer is good. If the resist is not good the final etch will also not be good.

DUV optimization

Dose test with the doses (J/m2): 200, 210, 220, 230, 240, 250, 270, 280 The aim was to get good line for 400nm pitch/200nm lines