Specific Process Knowledge/Lithography/EBeamLithography: Difference between revisions
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= | =Introduction to E-beam lithography at DTU Nanolab= | ||
DTU Nanolab has two EBL exposure systems, a JEOL JBX-9500FSZ and a Raith eLINE Plus system. The two systems are very different and new users should consult the EBL team to dertermine which system is appropriate for a particular project or type of sample. The general specifications of the two tools are given in the table below and may serve as a guideline for choice of system to use, especially the pros and cons list at the end of the table. | |||
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|style="background:LightGrey; color:black"|Min. electron beam size | |style="background:LightGrey; color:black"|Min. electron beam size | ||
|style="background:WhiteSmoke; color:black"|4 nm | |style="background:WhiteSmoke; color:black"|4 nm | ||
|style="background:WhiteSmoke; color:black"| | |style="background:WhiteSmoke; color:black"|10 nm | ||
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*1 x 6" wafer | *1 x 6" wafer | ||
*1 x 8" wafer | *1 x 8" wafer | ||
*Special | *Special chip cassette with slit openings of 20 mm (position A), 12 mm (position B), 8 mm (position C) and 4 mm (position D). | ||
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*Chips up to 75 x 75 mm | *Chips up to 75 x 75 mm | ||
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*Wafers with layers of silicon oxide or silicon (oxy)nitride | *Wafers with layers of silicon oxide or silicon (oxy)nitride | ||
*Wafers with layers of metal | *Wafers with layers of metal | ||
!style="background:silver; color:black" align="left" valign="top" rowspan="2"|General considerations | |||
|style="background:LightGrey; color:black"|Pros | |||
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*100 kV | |||
*Sub 10 nm resolution | |||
*Automatic beam optimization | |||
*High current and process speed | |||
*Automatic sample exchange | |||
*High level of programmability for automatic job execution | |||
*EBL workhorse for large designs | |||
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*Readily available | |||
*More intuitive software | |||
*Easier SEM mode alignment | |||
*Build in SEM automation for post exposure process control | |||
*2D stacks (HBN/graphene) allowed without Al coating | |||
*Excellent for small chips or small area design exposure | |||
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|style="background:LightGrey; color:black"|Cons | |||
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*Steep learning curve | |||
*Availability - booking calendar is usually full 5 weeks ahead | |||
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*Maximum 30 kV | |||
*User dependent performance/beam optimization | |||
*Minimum feature size >35 nm | |||
*Difficult to handle design files >1 GB | |||
*Slower writing speed | |||
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