Specific Process Knowledge/Lithography/EBeamLithography/FirstEBL: Difference between revisions

===My First E-Beam Lithography Process on the JEOL 9500===

The JEOL 9500 E-beam writer offers world class performance this however comes at a price of a fairly steep learning curve. This page is specifically intended to guide new users through their very first exposure on the system. In this guide we will set up a simple wafer/chip exposure. The complexity is kept at a relatively low level and we encourage new users to make sure their first job (first training session) matches this complexity level. More complex jobs can be run when a user is more familiar with the system.

Training on the JEOL 9500 system can be requested by sending a mail to [mailto:e-beam@nanolab.dtu.dk e-beam@nanolab.dtu.dk]. Please attach a process flow and any other relevant information for your process. Be advised that the booking calendar on the JEOL 9500 system is always very full, typically a user can expect the first training session about four weeks after the initial request.

The general workflow of E-beam lithography on the JEOL 9500 system is somewhat similar to that of UV lithography with a few added steps. The general workflow is

In the following we will look at each step in more detail and show step by step how to make a wafer/chip exposure.

DTU Nanolab offers a few different standard resist as given in the table below. Typically layers of 50-500 nm are applied. The Gamma UV & E-beam coater has predefined recipes for various thickness of CSAR resist. For other thickness or other resist the more manual Lab Spin 2 or 3 coasters can be used. If using the Lab Spin coaters please refer to the table below for information on thickness versus spin speed and soft bake temperature and baking time suggestions.

Resist thickness as function of spin speed on Lab Spin 2/3 can be estimated from the parameters above as y = ax^b, where y is resist thickness in nm and x is spin speed in RPM.

Electron beam exposure of non-conductive substrates will lead to a rapid and local build up of electrons and hence a build up of charge that will deflect the incident beam and distort the pattern writing. Non-conductive substrates can be coated with a metal film to provide sufficient conductance. A typical way to do this is to apply a 20 nm thermally evaporated Al layer on top of the resist layer. Please do not apply metals from e-beam evaporation sources as this process will to some extend exposure the resist with electrons from the metal evaporation process. Al is preferred due to its low atomic mass and hence minimum amount of forward beam scattering and also since it is very easy to etch away after e-beam exposure.

Since we are using a regular silicon wafer in our example job we will not need to apply a discharge layer.

Users will typically have their pattern in either CIF or GDS format. The JEOL 9500 system can only expose patterns defined in the v30 format and thus as a minimum the pattern must be translated to v30. This can be done with Beamer from Genisys. In this example job we will also show how to apply a Proximity Effect Correction (PEC) to the pattern, this is also done in Beamer.  

You can find a video demonstration of the procedure right here [link].

In order to execute the pattern writing a significant number of parameters must be defined for the job. These are defined in two text files; the Schedule Definition File (SDF) and Jobdeck Definition File (JDF). The system has a close to zero tolerance on syntax error from the user and thus these files should be prepared carefully, usually by using templates and correcting the parameters to suit your exposure. We encourage users to download and use SuperEdi for editing SDJ/JDF files. As the JEOL 9500 is operated from a Unix computer you must save your SDF/files in Unix format, available as a option from the “Save As” menu in SuperEdi.

Much more information on various commands in SDF/JDF files are available in the SDF and JDF file manual. [link]

At this stage we have a v30 file containing the pattern data and an SDF and JDF file describing the exposure parameters. These must be compiled into a magazine file (.mgn) which will completely define the exposure job.  

If compilation does not succeed the terminal will respond with a number of errors indicating which line(s) of the SDF or JDF file is causing the error.  

To ensure that the pattern and exposure parameters are correct one should always do a brief verification of the content of the .mgn file. From the right hand side of desktop two click on the “ACHECK” tool. From the window opening up choose “File” -> “Open” and open your magazine file.  

The JEOL 9500 system uses a proprietary sample cassette format and thus each sample must be mounted in an appropriate cassette. Cassettes are available for wafer sizes from 2” to 8”. Smaller chips must be mounted in dedicated chip cassettes with slots of four different sizes available. Slots are all 50 mm in width, the heights are 20, 12, 8 or 4 mm. A chip must have one side length at least 1 mm larger than the height such that it can safely be clamped in the slot. Thus the smallest possible chip to expose must have one side length of at least 5 mm.

***Any user found to violate this rule will be permanently excluded from using the JEOL 9500 system.***

Prior to exposure the chosen cassette has to be transferred from the auto stocker system and to the main chamber. This is done from the “Loader” module on the control computer

After cassette transfer the system has to be calibrated with the chosen beam current profile. This is done in a mostly automated sequence with only minute input from the user.

After exposure the discharge layer must be removed. In the case of thermal Al this is conveniently done using MIF 726, the UV developing agent found on both the “Gamma TMAH UV developer” and “TMAH manual developer” tools. The etch rate of thermal Al in MIF 726 is 30 nm/min. For etching a standard 20 nm thermal Al layer we recommend to choose a 60 s developer cycle on either tool.

Development of EBL resist can be done in two ways, either in beakers or on the automatic E-beam developer tool. The latter is equipped with ZED N50 for development of ZEP resist and AR 600-546 for development of CSAR. The system can handle chips or wafers up to 6”. It has predefined develop cycle times of 15, 30, 60 and 120 seconds.