Specific Process Knowledge/Lithography/EBeamLithography/FirstEBL: Difference between revisions

← Older edit Newer edit →

VisualWikitext

@@ Line 1: / Line 1: @@
 <span style="background:#FF2800">THIS PAGE IS UNDER CONSTRUCTION</span>[[image:Under_construction.png|200px]]
-===JEOL 9500: My First E-Beam Lithography Process===
+===My First E-Beam Lithography Process on the JEOL 9500===
-This page is a step by step guide to help new users through their '''first exposure''' on the JEOL 9500 system, (insert link to same page for Raith eLine Plus). In this guide we will set up an exposure job as an example. We will set it up as a dose test and hence keep it at a fairly low complexity level. The JEOL 9500 system has a steep learning curve and we encourage all users to keep the complexity level of their first exposure similar to the job in this guide.
+=Introduction=
+The JEOL 9500 E-beam writer offers world class performance this however comes at a price of a fairly steep learning curve. This page is specifically intended to guide new users through their very first exposure on the system. In this guide we will set up a simple wafer/chip exposure. The complexity is kept at a relatively low level and we encourage new users to make sure their first job (first training session) matches this complexity level. More complex jobs can be run when a user is more familiar with the system.
+General workflow
+The general workflow of E-beam lithography is somewhat similar to that of UV lithography with a few added steps. The general workflow is
-The job set up in this guide will go through the following steps
+*Resist coating and baking
-*Spin coating of e-beam resist
+*Application of discharge layer on substrates with >100 nm non-conducting films
-*Job file preparation
+*Pattern preparation, possibly including Proximity Effect Correction
-*Pattern preparation including Proximity Effect Correction
+*Jobdeck file (JDF) and schedule file (SDF) preparation
+*Job file compilation
+*Job file verification
+*Sample mounting
+*Cassette transfer
+*System calibration
 *Exposure
+*Cassette and sample unloading
+*Discharge layer removal
 *Development
+In the following we will look at each step in more detail and show step by step how to make a wafer/chip exposure.
 ==Spin coating of resist==
@@ Line 69: / Line 82: @@
 |}
-My first JEOL 9500 exposure
-Introduction
-The JEOL 9500 E-beam writer offers world class performance this however comes at a price of a fairly steep learning curve. This page is specifically intended to guide new users through their very first exposure on the system. In this guide we will set up a simple wafer/chip exposure. The complexity is kept at a relatively low level and we encourage new users to make sure their first job (first training session) matches this complexity level. More complex jobs can be run when a user is more familiar with the system.
-General workflow
-The general workflow of E-beam lithography is somewhat similar to that of UV lithography with a few added steps. The general workflow is
-Resist coating and baking
-Application of discharge layer on substrates with >100 nm non-conducting films
-Pattern preparation, possibly including Proximity Effect Correction
-Jobdeck file (JDF) and schedule file (SDF) preparation
-Job file compilation
-Job file verification
-Sample mounting
-Cassette transfer
-System calibration
-Exposure
-Cassette and sample unloading
-Discharge layer removal
-Development
-In the following we will look at each step in more detail and show step by step how to make a wafer/chip exposure.
 Resist coating