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Specific Process Knowledge/Etch/DRIE-Pegasus/Pegasus-2/Si Nano etching: Difference between revisions

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[[File:Fig 13d - 1.png|800px|left|thumb|'''''Notch-free nanostructures in SOI material derived from the fine-tuned CORE sequence.(Left) Grating with 80 nm periodicity. (Right) RIE lag test structure between 30 and 100 nm.''''']]
[[File:Fig 13d - 1.png|800px|left|thumb|'''''Notch-free nanostructures in SOI material derived from the fine-tuned CORE sequence.(Left) Grating with 80 nm periodicity. (Right) RIE lag test structure between 30 and 100 nm.''''']]


Silicon wafers are prepared with 1.5 μm thick resist patterns (AZ MIR 701 DUV resist from MicroChemicals) and exposed using a maskless aligner (MLA150, Heidelberg) to create patterns above 400 nm.  
Silicon wafers are prepared with 1.5 μm thick resist patterns (AZ MIR 701 DUV resist from MicroChemicals) and exposed using a maskless aligner (MLA150, Heidelberg) to create patterns above 400 nm.  
For nanosized patterns between 30 and 100 nm, an electron beam writing system (JEOL JBX-9500FSZ)  is used with positive tone e-beam resist ZEP520A (ZEON).
For nanosized patterns between 30 and 100 nm, an electron beam writing system (JEOL JBX-9500FSZ)  is used with positive tone e-beam resist ZEP520A (ZEON).


For more details, please contact Henri Jansen (henrija@dtu.dk) or Vy Thi Hoang Nguyen (vthongu@dtu.dk).
For more details, please contact Henri Jansen (henrija@dtu.dk) or Vy Thi Hoang Nguyen (vthongu@dtu.dk).