Specific Process Knowledge/Lithography/EBeamLithography: Difference between revisions

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	== Trilayer resist stack ==		== Trilayer resist stack ==
	As an alternative to PEC, a trilayer reists stack with a thin layer of thermally evaporated Ge can be used [http://avspublications.org/jvst/resource/1/jvstal/v19/i4/p1304_s1]. This reists stack has not yet been tested at DTU ~~Danchip~~. A process flow for this procedure can be found here [[media:Process_Flow_Trilayer_Ebeam_Resist.docx‎\|Process_Flow_Trilayer_Ebeam_Resist.docx‎]], but please contact [mailto:Lithography@nanolab.dtu.dk Lithography] before use.		As an alternative to PEC, a trilayer reists stack with a thin layer of thermally evaporated Ge can be used [http://avspublications.org/jvst/resource/1/jvstal/v19/i4/p1304_s1]. This reists stack has not yet been tested at DTU Nanolab. A process flow for this procedure can be found here [[media:Process_Flow_Trilayer_Ebeam_Resist.docx‎\|Process_Flow_Trilayer_Ebeam_Resist.docx‎]], but please contact [mailto:Lithography@nanolab.dtu.dk Lithography] before use.