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Both RIE's (RIE1 and RIE2) for silicon based etching has been decommissioned

Etching using the dry etch technique RIE (Reactive Ion Etch)

RIE2 (part of Cluster2)- positioned in clean room C-1

We had two RIE's. RIE2 for etching silicon based materials, resist and polymers and one (III-V RIE) for etching III-V materials. Here only RIE2 will be described.

In RIE2 it is allowed to have small amounts of metals exposed to the plasma.

The user manuals, quality control procedures and results, user APVs, technical information and contact information can be found in LabManager:

RIE2 info page in LabManager

Process information

Equipment performance and process related parameters

Equipment		RIE1 - HAS BEEN DECOMMISSIONED	RIE2
Purpose	Dry etch of	Silicon Silicon oxide Silicon (oxy)nitride Resist	Silicon Silicon oxide Silicon (oxy)nitride Resist and other polymers
Performance	Etch rates	Silicon: ~0.04-0.8 µm/min Silicon oxide: ~0.02-0.15 µm/min Silicon (oxy)nitride: ~0.02-? µm/min	Silicon: ~0.04-0.8 µm/min Silicon oxide: ~0.02-0.15 µm/min Silicon (oxy)nitride: ~0.02-? µm/min
Performance	Anisotropy	Can vary from isotropic to anisotropic with vertical sidewalls and on to a physical etch where the sidewalls are angled but without etching under the mask.	Can vary from isotropic to anisotropic with vertical sidewalls and on to a physical etch where the sidewalls are angled but without etching under the mask.
Process parameter range	Max pressure	800 mTorr	949 mTorr
	Max R.F. power	600 W	600 W
	Gas flows	SF₆: 0-52 sccm O₂: 0-99 sccm CHF₃: 0-100 sccm CF₄: 0-42 sccm Ar: 0-146 sccm N₂: 0-100 sccm C₂F₆: 0-24 sccm	SF₆: 0-130 sccm O₂: 0-99 sccm CHF₃: 0-99 sccm CF₄: 0-84 sccm Ar: 0-145 sccm N₂: 0-99 sccm
Substrates	Batch size	1 4" wafer 1 2" wafer (use Al carrier with Si dummy wafer) Several smaller samples (use Al carrier with Si dummy wafer)	1 4" wafer (use Al carrier with Si dummy wafer) 1 2" wafer (use Al carrier with Si dummy wafer) 1 6" wafer (requires 6" setup) Several smaller samples (use Al carrier with Si dummy wafer)
	Allowed materials	Silicon Silicon oxide (with boron, phosphorous and germanium) Silicon nitrides (with boron, phosphorous and germanium) Pure quartz, fused silica (not Pyrex, Tempax and other glasses) Resists: AZ resists, e-beam resists, SU8, DUV resists Aluminium as thin film layer on your sample	Silicon Silicon oxide (with boron, phosphorous and germanium) Silicon nitrides (with boron, phosphorous and germanium) Pure quartz, fused silica (not Pyrex, Tempax and other glasses) Resists: AZ resists, e-beam resists, SU8, DUV resists Other olymers (ask the Plasma group for permission) Aluminium as thin film layer on your sample Other metals (<5% coverage of the wafer)

@@ Line 10: / Line 10: @@
 -->
 [[image:Cluster2x.jpg|200x200px|right|thumb|RIE2 (part of Cluster2)- positioned in clean room C-1]]
-At Danchip we have now two RIE's. RIE2 for etching silicon based materials, resist and polymers and one (III-V RIE) for etching III-V materials. Here only RIE2 will be described.
+We had two RIE's. RIE2 for etching silicon based materials, resist and polymers and one (III-V RIE) for etching III-V materials. Here only RIE2 will be described.
 In RIE2 it is allowed to have small amounts of metals exposed to the plasma.
@@ Line 18: / Line 18: @@
 <!-- remember to remove the type of documents that are not present -->
-[http://labmanager.danchip.dtu.dk/function.php?module=Machine&view=view&mach=19 RIE2 info page in LabManager]
+[http://labmanager.dtu.dk/function.php?module=Machine&view=view&mach=19 RIE2 info page in LabManager]
 == Process information ==
@@ Line 138: / Line 138: @@
 [[image:Cluster1a.jpg|200x200px|right|thumb|RIE1 (part of cluster1) - positioned in cleanroom2]]
 [[image:Cluster2x.jpg|200x200px|right|thumb|RIE2 (part of cluster2)- positioned in cleanroom3]]
-At Danchip we have three RIE's. Two (RIE1 and RIE2) for etching silicon based materials (silicon, silicon oxide, silicon nitride) and one (III-V RIE) for etching III-V materials. The hardware of RIE1 and RIE2 is very similar but you cannot count on that identical recipes on RIE1 and RIE2 perform exactly the same. In addition to that the main difference between RIE1 and RIE2 is the cleanness of the two equipment. In rough terms RIE1 is the clean system and the RIE2 is the dirty system. This means that in RIE2 opposed to RIE1 it is allowed to have small amounts of metals exposed to the plasma. Look in the manuals for RIE1 and RIE2 to read the details for this difference (you can find the manuals in LabManager [http://labmanager.danchip.dtu.dk/function.php?module=Machine&view=view&mach=18 RIE1], [http://labmanager.danchip.dtu.dk/function.php?module=Machine&view=view&mach=19 RIE2]).
+We have three RIE's. Two (RIE1 and RIE2) for etching silicon based materials (silicon, silicon oxide, silicon nitride) and one (III-V RIE) for etching III-V materials. The hardware of RIE1 and RIE2 is very similar but you cannot count on that identical recipes on RIE1 and RIE2 perform exactly the same. In addition to that the main difference between RIE1 and RIE2 is the cleanness of the two equipment. In rough terms RIE1 is the clean system and the RIE2 is the dirty system. This means that in RIE2 opposed to RIE1 it is allowed to have small amounts of metals exposed to the plasma. Look in the manuals for RIE1 and RIE2 to read the details for this difference (you can find the manuals in LabManager [http://labmanager.dtu.dk/function.php?module=Machine&view=view&mach=18 RIE1], [http://labmanager.dtu.dk/function.php?module=Machine&view=view&mach=19 RIE2]).
 == Process information ==