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Line 86: Process log at Danchip [http://labintra.danchip.dtu.dk/index.php/Main_Page/Process_Logs/jmli/Pegasus]
Process log at Danchip [http://labintra.danchip.dtu.dk/index.php/Main_Page/Process_Logs/jmli/Pegasus]
==Equipment performance and process related parameters==
{| border="2" cellspacing="0" cellpadding="2"
!colspan="2" border="none" style="background:silver; color:black;" align="center"|Equipment
|style="background:WhiteSmoke; color:black"|<b>DRIE-Pegasus</b>
|-
!style="background:silver; color:black;" align="center" width="80"|Purpose
|style="background:LightGrey; color:black"| Dry etch of
|style="background:WhiteSmoke; color:black"|
* Silicon
* Barc
|-
!style="background:silver; color:black" align="center" valign="center" rowspan="2"|Performance
|style="background:LightGrey; color:black"|Etch rates
|style="background:WhiteSmoke; color:black"|
* Standard processes A and B up to 15 µm/min depending on etch load and feature size
* Other processes: Any number from 200 nm/min to 10 µm/min
|-
|style="background:LightGrey; color:black"|Uniformity
|style="background:WhiteSmoke; color:black"|
* For standard processes better than 3 % across a 150 mm wafer.
|-
!style="background:silver; color:black" align="center" valign="center" rowspan="4"|Process parameter range
|style="background:LightGrey; color:black"|RF powers
|style="background:WhiteSmoke; color:black"|
* Coil Power 5 kW
* Platen power 300/500 W (HF/LF)
|-
|style="background:LightGrey; color:black"|Gas flows
|style="background:WhiteSmoke; color:black"|
* SF<sub>6</sub>: 0 to 1200 sccm
* O<sub>2</sub>: 0 to 200 sccm
* C<sub>4</sub>F<sub>8</sub>: 0 to 400 sccm
* Ar: 0 to 283 sccm
|-
|style="background:LightGrey; color:black"|Pressure and temperature
|style="background:WhiteSmoke; color:black"|
* Pressure range 4 to 250 mTorr
* Temperature range -20 to 30 degrees C
|-
|style="background:LightGrey; color:black"|Process options
|style="background:WhiteSmoke; color:black"|
* Bosch processes with etch and dep cycles possibly split into three individually controllable parts
* Parameter ramping during process steps
* SOI option to reduce notching at buried
|-
!style="background:silver; color:black" align="center" valign="center" rowspan="3"|Substrates
|style="background:LightGrey; color:black"|Batch size
|style="background:WhiteSmoke; color:black"|
*<nowiki>#</nowiki> small samples on carriers
*<nowiki>#</nowiki> 50 mm wafers: Bonded to carriers
*<nowiki>#</nowiki> 100 mm wafers: Up to 18 wafers in a batch process
*<nowiki>#</nowiki> 150 mm wafers: 1 wafer
|-
| style="background:LightGrey; color:black"|Allowed materials
|style="background:WhiteSmoke; color:black"|
* Silicon wafers
* Quartz wafers need a (semi)conducting layer for clamping
|-
| style="background:LightGrey; color:black"|Possible masking materials
|style="background:WhiteSmoke; color:black"|
* AZ photoresist
* zep resist
* DUV stepper resist (barc + krf)
* Oxides and nitrides
* Aluminium (only very mild processes such as process C and nanoetches)
|}
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DRIE-Pegasus 1 The DRIE-Pegasus 1 load lock and cassette loader in the Danchip cleanroom A-1 The user manual(s), quality control procedure(s) and results, user APV(s), technical information and contact information can be found in LabManager:
Equipment info in LabManager
Process information SPTS process notation
Describing a process recipe on the Pegasus may sometimes be difficult because of the great flexibility of the instrument. A compact and precise notation is therefore required for the recipes. Click here to find a short description of the official SPTS notation.
Standard recipes
Hardware changes
A few hardware modifications have been made on the Pegasus since it was installed in 2010. The changes are listed below.
Other etch processes More processes, such as for DUV resist, are currently being developed, but they are not quite 'ready for publication' at LabAdviser so please contact Jonas (mailto:jml@danchip.dtu.dk ) for more information.
Advanced Processing - Henri Jansen style Wafer bonding To find information on how to bond wafers or chips to a carrier wafer, click here .
Acceptance test The instrument was opened for users in April 2010 when the acceptance test was signed. This was based on the performance of five standard recipes (A, B, C, D and SOI) that are further examined below. The acceptance test report is found here .
Characterisation of etched trenches
Comparing differences in etched trenches requires a set of common parameters for each trench. Click here to find more information about the parameters used on the DRIE-Pegasus process development.
Material from SPTS
Internal Danchip Process log
Process log at Danchip [1]
