Specific Process Knowledge/Etch/III-V ICP/InP-InGaAsP-InGaAs: Difference between revisions
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==InP etching June 2018== | ==InP etching June 2018== | ||
===Etching of an InP piece on Si carrier=== | ===Etching of an InP piece on Si carrier=== | ||
InP piece patterned with SiO2. The piece was etched on top of a Si wafer without bonding. The recipe "InP etch" was used. The roughness looks high in the bottom of the etched areas, especially the large open areas. | InP piece patterned with SiO2. The piece was etched on top of a Si wafer without bonding. The recipe "InP etch" was used. The roughness looks high in the bottom of the etched areas, especially in the large open areas. | ||
<gallery caption="Result of InP etching." widths="500px" heights="400px" perrow="3"> | <gallery caption="Result of InP etching." widths="500px" heights="400px" perrow="3"> | ||
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Image:S1_30dg_midt_11.jpg|closed look at the large roughness in the open areas. | Image:S1_30dg_midt_11.jpg|closed look at the large roughness in the open areas. | ||
</gallery> | </gallery> | ||
===Etching of an InP piece on SiO2 carrier=== | |||
InP piece patterned with SiO2. The piece was etched on top of a Si wafer coated with SiO2 without bonding. The recipe "InP etch" was used. The roughness looks low in the bottom of the etched areas, even in the large open areas. | |||