LabAdviser/Technology Research/Fabrication of Hyperbolic Metamaterials using Atomic Layer Deposition/AZO pillars: Difference between revisions

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====Procces flow description====
====Procces flow description====


=====Si template fabrication=====
Double side polished (DSP), 150 mm (100) Si wafers were selected for device fabrication. They were RCA cleaned and later oxidized in a conventional quartz tube (furnace from Tempress) using a dry oxidation process based on O<sup>2</sup> at 1100 °C, resulting in a 200 nm SiO<sup>2</sup> layer on Si. Next, a 2 μm amorphous Si layer was deposited on the SiO<sup>2</sup> surface using a conventional low-pressure chemical vapor deposition (LPCVD) process (furnace from
The whole fabrication work took place in a class 100 cleanroom. First, standard double side polished Si (100) wafers were selected and RCA cleaned (optional). Conventional deep-UV lithography (DUV stepper: Canon FPA-3000 EX4) was implemented for defining the grating patterns (lines 200 nm wide and 400 nm pitch) on 2x2 cm<sup>2</sup> scale chips. The normal procedure includes a bottom antireflective coating (BARC) and photoresist spinning, followed by spray developing. To promote adhesion and to minimize interference effects, the substrate surface was coated with a 65 nm thick BARC coating (DUV42S-6, Brewer Science, USA) followed by a bake-out at 175°C for 60 s. The positive photoresist (KRF M230Y, JSR Micro, NV) was spin-coated to a thickness of 360 nm and baked at 130°C for 90 s. Thereafter, deep reactive ion etching (DRIE) was used to fabricate trenches in the silicon substrate with a depth of 3 μm.
Tempress) based on SiH<sup>4</sup> at 560 °C. This procedure enables the preparation of home-made silicon-on-insulator (SOI) substrates.


=====Deep reactive ion etching=====
The main steps in the fabrication of pillars and tubes are shown in Fig 1. Initially, silicon holes were etched in SOI wafers by deep-UV lithography and DRIE (Fig. 1(a)-1(c)). The holes were arranged in a square lattice with the pitch of 400 nm. The template was then filled with an ALD D25 AZO coating (Fig. 1(d)) at 250 °C. The thickness of the deposited AZO depends on the desired output. An entire filling would result in the formation of pillars, while partial deposition leads to fabrication of hollow tubes. After removal of the top parts by Ar+ ion sputtering (Fig. 1(e)), the silicon core between the ALD coated holes was etched away during the last step. Figure 1(f) represents the final structures. Fabrication output is shown in Fig. 2. Each process step was carefully analyzed using cross-sectional SEM imaging (see Figs. 3 and 4 for tubes and pillars fabrication, respectively).
Three main steps were used in the Si template fabrication: etching of the BARC layer, high anisotropic silicon etching and resist removal. The BARC etch proceeds for 1 min using 40 sccm O2 plasma with coil and platen powers of 200 and 20 W, respectively. DRIE etching (DRIE-Pegasus from SPTS) proceeds in a switched process (Bosch process) consisting of cyclic steps of etching and surface passivation, with a process pressure of 10 mTorr. The processing substrate temperature was kept at 0°C. The trench depth was controlled by adjusting the number of cycles (150 cycles corresponds to 3 μm deep trenches). The last step in Si trench fabrication is the removal of the remaining resist. It was done by using O<sub>2</sub> plasma for 2 min with a gas flow of 100 sccm. The coil and platen powers were 800 and 20 W, respectively. The shape of the produced Si-template trench structures was carefully investigated by SEM in cross-sectional mode by sacrificing some of the prepared structures. Prior to the next step (ALD deposition) the prepared template structure received additional O<sub>2</sub>/N<sub>2</sub> plasma treatment in order to remove any possible organic residuals from resist coatings and surroundings.  


=====Atomic Layer Deposition=====
<gallery caption="" widths="500px" heights="600px" perrow="2">
The AZO coatings were made in a thermal, hot-wall ALD system (Picosun R200). The precursors were obtained from Strem Chemicals. ZnO was deposited using diethylzinc (Zn (C<sub>2</sub>H<sub>5</sub>)<sub>2</sub>, DEZ) and deionized water (H<sub>2</sub>O), whereas Al doping of the ZnO was introduced by a single cycle of trimethylaluminium (Al(CH<sub>3</sub>)<sub>3</sub>, TMA) and H<sub>2</sub>O into a ZnO matrix made by 20 cycles of “DEZ +H<sub>2</sub>O”. This defines an AZO macrocycle: 20 cycles of “DEZ+H<sub>2</sub>O” and one cycle of “TMA+H<sub>2</sub>O”. The deposition temperature was kept constant at 200°C. Approximately 55 AZO macrocycles need to be deposited in order to fill the Si trench template entirely.
image:Figure 1. Fabrication_shematic_AZO_pillars_eves2.jpg| Schematics of the fabrication flow. a) Home-made SOI substrates. b) Deep-UV lithography. Resist spin coating, baking, exposure and developing. c) DRIE etching, fabrication of initial Si template. d) ALD deposition of D25 AZO at 250 °C. Partial deposition will lead to fabrication of tubes, while complete filling will create full pillars. e) Removal of the top AZO layer by Ar+ sputtering. f) Silicon host removal using conventional RIE process.
 
image:Figure 2. AZO_structures_fab_supplementary_eves.jpg| SEM images, bird-eye-view. a) AZO pillars and b) AZO tubes.
=====Top layer removal and selective etch of the Si template=====
In order to get rid of the deposited top layer of AZO and to gain access to the Si template core, a pure physical etching with Ar<sup>+</sup> ions (Ionfab 300 plus from Oxford Instruments) was used. Here, the process was tuned to an etch rate of 20 nm/min which provided a well-controlled top layer breakthrough. Following this, the subsequent selective silicon etching (template removal) proceeded using a continuous isotropic etch in a reactive ion etching tool (RIE, from SPTS) based on SF<sub>6</sub> at a substrate temperature of 20°C. The SF<sub>6</sub> gas flow was kept constant at 35 sccm at a process pressure of 80 mTorr. The coil power was set to 30W. This process proceeds with an extreme selectivity towards the deposited AZO without any observable harm on the prepared AZO grating structure. Controlling the etch time is crucial, since prolongation of the etching will result in a collapse of the AZO gratings. 18 min of Si etching was required to fabricate a free standing, separated AZO grating with a minimal amount of the Si core between the AZO lamellas needed to support the grating skeleton.
 
 
<gallery caption="" widths="500px" heights="600px" perrow="1">
image:Fabrication_shematic_AZO_pillars_eves2.jpg| Scheme of fabrication flow. High aspect ratio AZO nanopillars and tubes.
</gallery>
</gallery>
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<gallery caption="" widths="500px" heights="600px" perrow="3">
<gallery caption="" widths="500px" heights="600px" perrow="2">
image:AZO_pillars_fab_supplementary_eves.jpg| Scheme of fabrication flow. SEM inspection.
image:Figure 3. AZO_tubes_fab_supplementary_eves.jpg| Scheme of fabrication flow. SEM inspection.
image:AZO_tubes_fab_supplementary_eves.jpg| Scheme of fabrication flow. SEM inspection.
image:figure 4. AZO_pillars_fab_supplementary_eves.jpg| Scheme of fabrication flow. SEM inspection.
image:AZO_structures_fab_supplementary_eves.jpg| SEM images, bird-eye-view. a) AZO pillars and b) AZO tubes.
</gallery>
</gallery>

Revision as of 19:05, 15 March 2017

Procces flow description

Double side polished (DSP), 150 mm (100) Si wafers were selected for device fabrication. They were RCA cleaned and later oxidized in a conventional quartz tube (furnace from Tempress) using a dry oxidation process based on O2 at 1100 °C, resulting in a 200 nm SiO2 layer on Si. Next, a 2 μm amorphous Si layer was deposited on the SiO2 surface using a conventional low-pressure chemical vapor deposition (LPCVD) process (furnace from Tempress) based on SiH4 at 560 °C. This procedure enables the preparation of home-made silicon-on-insulator (SOI) substrates.

The main steps in the fabrication of pillars and tubes are shown in Fig 1. Initially, silicon holes were etched in SOI wafers by deep-UV lithography and DRIE (Fig. 1(a)-1(c)). The holes were arranged in a square lattice with the pitch of 400 nm. The template was then filled with an ALD D25 AZO coating (Fig. 1(d)) at 250 °C. The thickness of the deposited AZO depends on the desired output. An entire filling would result in the formation of pillars, while partial deposition leads to fabrication of hollow tubes. After removal of the top parts by Ar+ ion sputtering (Fig. 1(e)), the silicon core between the ALD coated holes was etched away during the last step. Figure 1(f) represents the final structures. Fabrication output is shown in Fig. 2. Each process step was carefully analyzed using cross-sectional SEM imaging (see Figs. 3 and 4 for tubes and pillars fabrication, respectively).


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