Specific Process Knowledge/Lithography/EBeamLithography

JEOL JBX-9500 E-beam writer positioned in room E-2

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The JEOL JBX-9500 electron beam lithography system is a spot electron beam type lithography system designed for writing patterns with dimensions from nanometers to sub-micrometers. The minimum electron beam is around 5 nm, the maximum writitng field without stitching is 1 mm x 1 mm.

The machine is located in a class 10 cleanroom (E-2) with tight temperature and moisture control. The room must only be entered when the machines or equipment inside the room is intended to be used.

You can read more about electron beam writing in this book published by SPIE.

The user manual, technical information and contact information can be found in LabManager and LabAdviser:

1. E-beam writer in LabManager
2. User manual for JBX-9500 e-beam writer on LabAdviser
3. BEAMER Manual on LabAdviser
4. Sdf- and jdf file preparation manual on LabAdviser

Performance of the e-beam writers at DTU Danchip

Purpose	pattern an electron sensitive resist	Mainly for pattering structures with minimum feature size between 12 nm - 1 µm
Performance	Resolution	~5 nm beam diameter, ~10 nm lines obtained in 50 nm thick resist (CSAR)
	Maximum writing area without stitching	1mm x 1mm
Process parameter range	E-beam voltage	100kV
	Scanning speed	100MHz
	Min. electron beam size	5nm
	Min. step size	1nm
	Beam current range	0.1nA to 60nA in normal conditions (see available condition files here)
	Dose range	0.001µC/cm2 to 100000µC/cm2
Samples	Batch size	Wafer cassettes: 6 x 2" wafers 2 x 4" wafers 1 x 6" wafer Special wafer cassette with slit openings of 20 mm (position A), 12 mm (position B), 8 mm (position C) and 4 mm (position D).
	Substrate material allowed	Silicon, quartz, pyrex, III-V materials Wafers with layers of silicon oxide or silicon (oxy)nitride Wafers with layers of metal

Getting started

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To request for an e-beam training session, contact e-beam@danchip.dtu.dk; a DTU Danchip personnel will hereafter provide a time slot. Users require at least 4 training sessions before being allowed full acccess to the machine. The first training will focus on file preparation and compilation alone.

It takes several months to get full authorization to the machine. Therefore, if you are either in a hurry, or a visiting researcher, or only require a few e-beam exposures to fulfill your project, let one of your authorized colleagues expose for you.

Before you request for a training on the machine, fulfill the following steps:

Prepare a v30-file:

1. Prepare your pattern using a layout software (L-edit, CleWin, CAD) and export that to GDS format. Check your GDS-file by importing it in e.g. CleWin or L-edit. In order to reach the files from the computers inside the cleanroom it is recommended to either dropbox them or send them per email to yourself.
2. Convert the GDS file to v30 using BEAMER; a manual for BEAMER software is found here

Create sdf and jdf-files:

1. download SuperEdi,
2. read the sdf and jdf-file manual found here,
3. find templates of sdf and jdf files on the cleanroom drive in the folder E-beam sdf and jdf templates.

Gather Experience

1. Assist a fully trained colleague of yours when she or he e-beam writes, gather as much knowledge about your e-beam run, i.e. which e-beam current, aperture and dose to use, which shot pitch (e.g. SHOT A,10).
2. Study the logbook for the e-beam writer: sheet 1 gives you an overview of which condition files (currents and apertures) have been in use recently by which user on which type of resist. On sheet 2 in this logbook you can find a writing time estimation program.
3. Study the manual for the machine, it can be found here

General Rules

For safety reasons, even fully trained users are only authorized to mount substrates into the e-beam cassettes, but not authorized to load the cassettes into the autoloader.

To use the e-beam writer, book the machine via LabManager, note the number and type of substrate as well as the condition file to be used in the 'Public Comment:' field in LabManager. Mount your substrate in the cassette and pre-align if necessary. Call for help from DTU Danchip staff to load your cassette into the robot loader (the autoloader).

After your exposure, fully trained users can unload their cassettes from the autoloader, unmount their substrates and re-load an empty cassette into the autoloader. If you are unable to unmount your substrates before another user requires the cassette, you must accept that either the next user or DTU Danchip personel unmount your substrates.

E-beam resists and Process Flows

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The table describes the e-beam resist used in the cleanroom for standard e-beam exposure. Some of resists are not provided by DTU Danchip and some are not yet approved for common use in the cleanroom and are currently being tested. If you wish to test some of these resists or other resists, please contact Lithography.

Standard DTU Danchip resists purchased and tested by DTU Danchip:

Resist	Polarity	Manufacturer	Comments	Technical reports	Spin Coater	Thinner	Developer	Rinse	Remover	Process flows (in docx-format)
CSAR	Positive	AllResist	Standard positive resist, very similar to ZEP520.	Allresist_CSAR62_English.pdf‎,, CSAR_62_Abstract_Allresist.pdf‎	See table here	Anisole	AR-600-546, AR-600-548, N50, MIBK:IPA	IPA	AR-600-71, 1165 Remover	Process Flow CSAR.docx‎ Process Flow CSAR with ESPACER Process Flow CSAR with Al
ZEP520A	Positive resist, contact Lithography if you plan to use this resist	ZEON	Positive resist	ZEP520A.pdf, ZEP520A spin curves on SSE Spinner	See table here	Anisole	ZED-N50/Hexyl Acetate,n-amyl acetate, oxylene. JJAP-51-06FC05.pdf‎, JVB001037.pdf‎	IPA	acetone/1165	Process_Flow_ZEP.docx
Copolymer AR-P 617	Positive	AllResist	Approved, not tested yet. Used for trilayer (PEC-free) resist-stack or double-layer lift-off resist stack. Please contact Lithography for information.	AR_P617.pdf‎	See table here	PGME	AR 600-55, MIBK:IPA		acetone/1165	Trilayer stack: Process_Flow_Trilayer_Ebeam_Resist.docx‎
mr EBL 6000.1	Negative	MicroResist	Standard negative resist	mrEBL6000 processing Guidelines.pdf‎	See table here	Anisole	mr DEV	IPA	mr REM	Process_Flow_mrEBL6000.docx‎
HSQ (XR-1541)	Negative	DOW Corning	Approved. Standard negative resist, mainly for III-V materials		See table here		TMAH, AZ400K:H2O	H2O
AR-N 7520	Negative	AllResist	Both e-beam, DUV and UV-sensitive resist. Currently being tested, contact Peixiong Shi for information.	AR-N7500-7520.pdf‎	See table here	PGMEA	AR 300-47, TMAH	H2O

Non-standard DTU Danchip resists not purchased by DTU Danchip:

Resist	Polarity	Manufacturer	Comments	Technical reports	Spinner	Thinner	Developer	Rinse	Remover	Process flows (in docx-format)
PMMA	Positive	AllResist	We have various types of PMMA in the cleanroom. Please contact Lithography for information.		See table here		MIBK:IPA (1:3), IPA:H2O	IPA	acetone/1165/Pirahna
ZEP7000	Positive	ZEON	Not approved. Low dose to clear, can be used for trilayer (PEC-free) resist-stack. Please contact Lithography for information.	ZEP7000.pdf	See table here		ZED-500/Hexyl Acetate,n-amyl acetate, oxylene.	IPA	acetone/1165	Trilayer stack: Process_Flow_Trilayer_Ebeam_Resist.docx‎

Cassettes

Authorized users are allowed to unload a cassette from the robot loader (autoloader) and mount their substrate but not allowed to load the cassette into the loader after mount.

We have one chip cassette, 2 2" cassettes, 2 4" cassettes, many 6" cassettes and 1 8" cassette. Some cassettes are made of Aluminum, others of Titanium. The thermal expansion coefficient of Ti is much lower than of Al; bear this in mind if you have crucial patterns to expose.

Keep an eye on the wafer orientation when you mount; the 2" aluminum cassette still have wafer orientation flat-up.

chip Al/Cu cassette with slot widths of 20 mm, 12 mm, 8 mm and 4 mm	2" Ti cassette; wafer orientation is flat-down	2" Al cassette; wafer orientation is flat-up	4" Ti cassette; wafer orientation is flat-down	4" Al cassette; wafer orientation is flat-down

Alignment of exposure to existing pattern on wafer

If you need to align an exposure to an existing pattern on a wafer you need wafer marks (or global marks) to align your exposure to. If you are exposing chips (i.e. many small GDS-files you repeat in a matrix), chip marks is recommended to align every chip.

Please note that manual alignment (using the SEM) is not allowed. You should use semi-automatic alignment only. In rare cases where semi-automatic alignment is impossible, you should remove the resist around the wafer marks before loading the wafer/chip into the machine.

Definition of length and width of global mark, use L = 500-1000 µm, W 3-5 µm	Text around mark not recommended	Global mark (P and Q) positions on wafer. Positions of global marks are entered in jdf file using wafer coordinate system.	Example of chip with 4 chip marks. Always position the chip marks outside the chip pattern. Position of chip marks are entered in jdf file using chip coordinate system, i.e. center of chip is (0,0).

1 Material: Global marks or chip marks should be clearly visible in a 100keV SEM, i.e. preferably defined by Ti/Au or another 'heavy' metal, alternatively the wafer marks should be etched. In Si, etched mark should be around 1 µm deep in order to be detectable by the machine. Shallow etched (even 200 nm etched profiles) global marks or global marks in Si or marks defined by a light metal as Al can be hard to locate manually as well as automatically by the machine.

2 Design:

• Global marks: You need at least two wafer marks, a P mark and a Q mark. It is recommended to have many P and Q marks available on the wafer to choose from. The x-coordinate of the P mark should be smaller than the x-coordinate of the Q mark. The global marks should either be crosses or L-shaped, they should be as narrow as possible and 500 - 1000 microns in length. If the wafer contains a number of identical marks, the marks should be marked in order to identify the 'right' alignment mark (the scan width of the SEM is 1 mm x 1 mm). Text around the wafer mark is NOT recommended. Wafer marks formed as crosses with lengths of 1000 microns and 3-5 microns in width are recommended.
• Chip marks: Prepare 1 or 4 chip marks on every chip. The chip marks can be smaller than global marks, as only very fine alignment is performed with chip marks. The chip marks should either be crosses or L-shaped and text around the marks is NOT recommended.

Field stitching

In this experiment, several writing fields (1 mm x 1 mm) were stitched together. Vernier scales on the edges of each writing field shows the field stitching bewteen fields.

wafer 11.17 Stitching accuracy, Processed by TIGRE, April 2015
Resist	E-beam exposure	Development	Metallisation	Lift-off	Characterisation
CSAR AR-P6200 AllResist, 4000 rpm, 60s, softbaked 60s @ 150degC	JBX9500 E-2, 2nA aperture 5, dose 300 µC/cm2, L1: 1st set of Vernier scales on edges (North, Upper Right, East, Lower Right, South, Lower Left, West, Upper Left) of entire writi9ng field	AR-600-546, 60 s	5 nm Ti, 45 nm Au, Wordentec (D-2)	AR-600-71, 5-10 min, 4s ultrasonic (D-3)	Zeiss Supra 60VP, 10kV, Inlens detector

Overlay accuracy (layer to layer stitching)

In this experiment, a set of Vernier marks (L1) were exposed along with global marks and chip marks in appr 170 nm CSAR. This layer was developed, metalized and lift-off. A new layer of resist (appr 170 nm CSAR) was spin coated onto the wafer. A second set of Vernier marks (L2) was aligned to two gloabl marks and 4 chip marks and exposed. Layer 2 was developed, metalized and lift-off. The final pattern SEM inspected in Zeiss Supra 60VP.

wafer 11.17 Stitching accuracy, Processed by TIGRE, April 2015
Resist	E-beam exposure	Development	Metallisation	Lift-off	Characterisation
CSAR AR-P6200 AllResist, 4000 rpm, 60s, softbaked 60s @ 150degC	JBX9500 E-2, 2nA aperture 5, dose 300 µC/cm2, L1: 1st set of Vernier scales, 6 global marks and 4 chip marks in every chip	AR-600-546, 60 s	5 nm Ti, 45 nm Au, Wordentec (D-2)	AR-600-71, 5-10 min, 4s ultrasonic (D-3)
CSAR AR-P6200 AllResist, 4000 rpm, 60s, softbaked 60s @ 150degC	JBX9500 E-2, 2nA aperture 5, dose 300 µC/cm2, L2: 2nd set of Vernier scales aligned to 2 global marks and 4 chip marks in every chip (scan width 10 µm)	AR-600-546, 60 s	5 nm Ti, 45 nm Au, Wordentec (D-2)	AR-600-71, 5-10 min, 4s ultrasonic (D-3)	Zeiss Supra 60VP, 10kV, Inlens detector

The Vernier scales were distributed over the entire writing field: C = center, UR/LR/LL/UL = Upper/Lower Right/Left, MN/ME/MS/MW = Middle North/East/South/West.

Proximity Error Correction

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Even though the electron beam diameter is below 5 nm, the feature and pitch resolution in resist is limited by the forward and backward scattering of the electrons. The forward scattering depends on the electron acceleration voltage, the resist material and thickness. The backward scattering depends on the electron acceleration voltage and the substrate material [1], [2].

As the travel distance of backscattered electrons is fairly large, e-beam patterned structures will be influenced by adjacent e-beam patterned structures, i.e. a proximity effect. These proximity effects can be avoided either by simulating a proximity error correction (PEC) in BEAMER or by using the right stack of e-beam resist.

Proximity Error Correction (PEC) in BEAMER

BEAMER is endowed with a software that corrects for proximity errors in the e-beam exposure. You can read more about this function in the BEAMER manual here and in the BEAMER presentation here BEAMERPresentation.pdf‎.

The proximity error correction require a forward and a backward range parameter, alfa and beta, and a ratio of backscattered energy to the forward scattered energy, eta. As alfa depends on the electron acceleration voltage, which is constant at 100kV, alfa is in BEAMER fixed to 0.007. Help to find beta and eta can be found here.

Alternatively, a point-spread function can be used in BEAMER to calculate the optimised dose-variation.

Trilayer resist stack

As an alternative to PEC, a trilayer reists stack with a thin layer of thermally evaporated Ge can be used [3]. This reists stack has not yet been tested at DTU Danchip. A process flow for this procedure can be found here Process_Flow_Trilayer_Ebeam_Resist.docx‎, but please contact Lithography before use.

Charging of non-conductive substrates

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All substrates are grounded to the cassette when properly loaded. In a non-conducting substrate, the accumulation of charges in the substrates will however destroy the e-beam patterning. To avoid this, a charge dissipating layer is added on top of the e-beam resist; this will provide a conducting layer for the electrons to escape, while high-energy electrons will pass through the layer to expose the resist.

If you wish to investigate the charge dissipation using other methods than below, please contact Lithography.

ESPACER

Espacer is a chemical that works as a discharging layer; it is spun onto the wafer on top of the resist and easily rinsed off the wafer after e-beam exposure. Visit this page for more information: Espacer

Aluminum coating

At DTU Danchip, we recommend to use a thin (20 nm) layer of thermally evaporated aluminum on top of the e-beam resist. Preferably, the thickness of Al and the e-beam dose should be optimised to the features you wish to e-beam pattern [4]. A good starting point is 20 nm Al; from here dose and development can be optimised to reach the resolution and feature size required.

The process flow for a standard e-beam exposure on ZEP520 with Al on top can be found here Process_Flow_ZEP_with_Al.docx‎.