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Specific Process Knowledge/Lithography/CSAR: Difference between revisions

Tigre (talk | contribs)
Tigre (talk | contribs)
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|Full 4" Si wafer with non-patterned ~180 nm CSAR
|Full 4" Si wafer with non-patterned ~180 nm CSAR
|nano1.42
|~56.5 (based on 2 runs)
|~56.5 (based on 2 runs)
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|Full 4" Si wafer with non-patterned ~240 nm CSAR, <br>postbaked 60 sec @ 130 degC
|Full 4" Si wafer with non-patterned ~240 nm CSAR, <br>postbaked 60 sec @ 130 degC
|nano1.42
|~56.5 (based on 2 runs)
|~56.5 (based on 2 runs)
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|1/4 4" Si wafer with non-patterned ~125 nm CSAR, <br>not crystal bonded to carrier
|1/4 4" Si wafer with non-patterned ~125 nm CSAR, <br>not crystal bonded to carrier
|nano1.42
|~83.3 (based on 3 runs)
|~83.3 (based on 3 runs)
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|1/4 4" Si wafer with non-patterned ~125 CSAR, <br>crystal bonded to 4" Si carrier
|1/4 4" Si wafer with non-patterned ~125 CSAR, <br>crystal bonded to 4" Si carrier
|nano1.42
|~54 (based on 1 run)
|~54 (based on 1 run)
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