Specific Process Knowledge/Etch/DRIE-Pegasus

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The DRIE Pegasus at Danchip

The SPTS Pegasus in the Danchip cleanroom A-1

The Bosch process

The DRIE Pegasus is a state-of-art silicon dry etcher that offers outstanding performance in terms of etch rate, uniformity etc. It uses the so-called Bosch process to achieve excellent control of the etched features. Click here for more fundamental information of the system.

The user manual(s), quality control procedure(s) and results, user APV(s), technical information and contact information can be found in LabManager:

Equipment info in LabManager

Process information

Process notation

Describing a process recipe on the Pegasus may sometimes be difficult because of the great flexibility of the instrument. A compact and precise notation is therefore required for the recipes. Click here to find a short description of the official SPTS notation.

Standard recipes

• Process A (Large trench): 80 µm wide trench etched down to a depth of 150 µm

• Process B (Via etch): 30 µm diameter via etched down to a depth of 100 µm

• Process C (Nano etch): 50-300 nm posts

• Process D (Micro stamp):

• SOI etch

Other etch processes

• Nanoetch

More processes, such as for DUV resist, are currently being developed, but they are not quite 'ready for publication' at LabAdviser so please contact Jonas (mailto:jml@danchip.dtu.dk) for more information.

Equipment performance and process related parameters

Equipment		DRIE-Pegasus
Purpose	Dry etch of	Silicon Barc
Performance	Etch rates	Standard processes A and B up to 15 µm/min depending on etch load and feature size Other processes: Any number from 200 nm/min to 10 µm/min
	Uniformity	For standard processes better than 3 % across a 150 mm wafer.
Process parameter range	RF powers	Coil Power 5 kW Platen power 300/500 W (HF/LF)
	Gas flows	SF6: 0 to 1200 sccm O2: 0 to 200 sccm C4F8: 0 to 400 sccm Ar: 0 to 283 sccm
	Pressure and temperature	Pressure range 4 to 250 mTorr Temperature range -20 to 30 degrees C
	Process options	Bosch processes with etch and dep cycles possibly split into three individually controllable parts Parameter ramping during process steps SOI option to reduce notching at buried
Substrates	Batch size	# small samples on carriers # 50 mm wafers: Bonded to carriers # 100 mm wafers: Up to 18 wafers in a batch process # 150 mm wafers: 1 wafer
	Allowed materials	Silicon wafers Quartz wafers need a (semi)conducting layer for clamping
	Possible masking materials	AZ photoresist zep resist DUV stepper resist (barc + krf) Oxides and nitrides Aluminium (only very mild processes such as process C and nanoetches)

Additional information

Wafer bonding

To find information on how to bond wafers or chips to a carrier wafer, click Template:TemporaryBonding

here.

Acceptance test

The instrument was opened for users in April 2010 when the acceptance test was signed. This was based on the performance of five standard recipes (A, B, C, D and SOI) that are further examined below. The acceptance test report is found here.

Characterisation of etched trenches

Comparing differences in etched trenches requires a set of common parameters for each trench. Click here to find more information about the parameters used on the DRIE-Pegasus process development.

Material from SPTS

• Hardware and process applications

• Miscellaneous information

Internal Danchip Process log

Process log at Danchip [1]