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Specific Process Knowledge/Lithography/CSAR: Difference between revisions

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DCH-Employees-701
2,257 edits
Tigre (talk | contribs)
DCH-Employees-701
2,257 edits
Line 697: Line 697:
|4" Si wafer with non-patterned CSAR
|4" Si wafer with non-patterned CSAR
|nano1.42
|nano1.42
|56.5 nm/min (based on 2 runs)
|56.5 (based on 2 runs)
|
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Line 703: Line 703:
|4" Si wafer with non-patterned CSAR, postbaked 60 sec @ 130 degC
|4" Si wafer with non-patterned CSAR, postbaked 60 sec @ 130 degC
|nano1.42
|nano1.42
|56.5 nm/min (based on 2 runs)
|56.5 (based on 2 runs)
|
|
|-
|-
Line 709: Line 709:
|1/4 4" Si wafer with non-patterned CSAR, not crystal bonded to carrier
|1/4 4" Si wafer with non-patterned CSAR, not crystal bonded to carrier
|nano1.42
|nano1.42
|83.3 nm/min (based on 3 runs)
|83.3 (based on 3 runs)
|
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|-
|-
Line 715: Line 715:
|1/4 4" Si wafer with non-patterned CSAR, crystal bonded to 4" Si carrier
|1/4 4" Si wafer with non-patterned CSAR, crystal bonded to 4" Si carrier
|nano1.42
|nano1.42
|54 nm/min (based on 1 run)
|54 (based on 1 run)
|
|
|-
|-
Line 721: Line 721:
|Slice Si wafer with nano-patterned CSAR, crystal bonded to 4" Si carrier
|Slice Si wafer with nano-patterned CSAR, crystal bonded to 4" Si carrier
|nano1.42
|nano1.42
|54 nm/min (based on 1 run)
|54 (based on 1 run)
|
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|-
|-
|}
|}
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