Specific Process Knowledge/Thermal Process/C3 Anneal-bond furnace: Difference between revisions
Line 60: | Line 60: | ||
*Silicon wafers with layers of silicon oxide or silicon (oxy)nitride (RCA cleaned) | *Silicon wafers with layers of silicon oxide or silicon (oxy)nitride (RCA cleaned) | ||
*Wafers from the LPCVD furnaces | *Wafers from the LPCVD furnaces | ||
*Wafers from EVG NIL(assuming they were clean and not have been exposed to any metal when entering EVG NIL) | *Wafers from EVG NIL (assuming they were clean and not have been exposed to any metal when entering the EVG NIL) | ||
|- | |- | ||
|} | |} |
Revision as of 09:59, 13 January 2014
Feedback to this page: click here
Anneal-bond furnace (C3)
The Anneal-bond furnace (C3) is a Tempress horizontal furnace for oxidation and annealing of new and processed (bonded) silicon wafers.
This furnace is the third furnace tube in the furnace C-stack positioned in cleanroom 2.
In this furnace it is allowed oxidize and anneal wafers without doing an RCA clean first. Also bonded wafers comming directly from the EVG NIL (assuming they were clean and not have been exposed to any metal when entering EVG NIL) can be processed in the furnace. Check the cross contamination information in LabManager before you use the furnace.
The user manual, technical information and contact information can be found in LabManager:
Process knowledge
Purpose |
|
Oxidation:
|
---|---|---|
Performance | Film thickness |
|
Process parameter range | Process temperature |
|
Process pressure |
| |
Gas flows |
| |
Substrates | Batch size |
|
Substrate materials allowed |
|