Specific Process Knowledge/Thermal Process/C3 Anneal-bond furnace: Difference between revisions

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Anneal-bond furnace (C3)

The Anneal-bond furnace (C3) is a Tempress horizontal furnace for oxidation and annealing of new and processed (bonded) silicon wafers.

This furnace is the third furnace tube in the furnace C-stack positioned in cleanroom 2.

In this furnace it is allowed oxidize and anneal wafers without doing an RCA clean first. Also bonded wafers comming directly from the EVG NIL (assuming they were clean and not have been exposed to any metal when entering EVG NIL). Check the cross contamination information in LabManager before you use the furnace.

The user manual, technical information and contact information can be found in LabManager:

Anneal-bond Furnace (C3)

Process knowledge

Oxidation: look at the Oxidation page
Annealing: look at the Annealing page

Overview of the performance of Anneal Bond furnace and some process related parameters

Purpose	Oxidation of Si wafers Annealing of processed wafer, eg. bonded wafers	Oxidation: Dry Wet: with bubbler (water steam + N₂)
Performance	Film thickness	Dry SiO₂: 50 Å to ~2000 Å (it takes too long to grow a thicker oxide) Wet SiO₂: 50 Å to ~5 µm (it takes too long to grow a thicker oxide)
Process parameter range	Process temperature	800-1150 ^oC
	Process pressure	1 atm
	Gas flows	N₂: 5 sccm O₂: 5 sccm
Substrates	Batch size	1-30 100 mm wafers (or 50 mm wafers) per run
Substrates	Substrate materials allowed	Silicon wafers (new wafers or RCA cleaned wafers) Silicon wafers with layers of silicon oxide or silicon (oxy)nitride (RCA cleaned) Wafers from the LPCVD furnaces Wafers from EVG NIL(assuming they were clean and not have been exposed to any metal when entering EVG NIL)

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 ==Overview of the performance of Anneal Bond furnace and some process related parameters==
-{| border="2" cellspacing="0" cellpadding="0"
+{| border="2" cellspacing="0" cellpadding="2"
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 !style="background:silver; color:black;" align="center"|Purpose
@@ Line 37: / Line 37: @@
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 !style="background:silver; color:black" align="center" valign="center" rowspan="3"|Process parameter range
-|style="background:LightGrey; color:black"|Process Temperature
+|style="background:LightGrey; color:black"|Process temperature
 |style="background:WhiteSmoke; color:black"|
 *800-1150 <sup>o</sup>C
@@ Line 53: / Line 53: @@
 |style="background:LightGrey; color:black"|Batch size
 |style="background:WhiteSmoke; color:black"|
-*1-30 4" wafer (or 2" wafers) per run
+*1-30 100 mm wafers (or 50 mm wafers) per run
 |-
-|style="background:LightGrey; color:black"|Substrate material allowed
+|style="background:LightGrey; color:black"|Substrate materials allowed
 |style="background:WhiteSmoke; color:black"|
-*Silicon wafers (new from the box or RCA cleaned)
+*Silicon wafers (new wafers or RCA cleaned wafers)
 *Silicon wafers with layers of silicon oxide or silicon (oxy)nitride (RCA cleaned)
-*Quartz wafers (RCA cleaned)
+*Wafers from the LPCVD furnaces
-*From bonding in EVG NIL directly (assuming they were clean and not contain any metal when entering EVG NIL)
+*Wafers from EVG NIL(assuming they were clean and not have been exposed to any metal when entering EVG NIL)
 |-
 |}