Specific Process Knowledge/Thermal Process/C1 Furnace Anneal-oxide: Difference between revisions
No edit summary |
|||
| Line 2: | Line 2: | ||
==Anneal-oxide furnace (C1)== | ==Anneal-oxide furnace (C1)== | ||
[[Image:C1.JPG|thumb|300x300px| | [[Image:C1.JPG|thumb|300x300px|Anneal-oxide furnace (C1). Positioned in cleanroom 2]] | ||
The Anneal-oxide furnace (C1) is a Tempress horizontal furnace for oxidation and annealing of silicon wafers, e.g with layers of oxide, polysilicon or BPSG glass (from PECVD2). Both 100 mm and 150 mm wafers can be processed in the furnace. | The Anneal-oxide furnace (C1) is a Tempress horizontal furnace for oxidation and annealing of silicon wafers, e.g with layers of oxide, polysilicon or BPSG glass (from PECVD2). Both 100 mm and 150 mm wafers can be processed in the furnace. | ||
The Anneal-oxide furnace is the upper furnace tube in the furnace C-stack positioned in cleanroom 2. All wafers have to be RCA cleaned before they enter the furnace, the only | The Anneal-oxide furnace is the upper furnace tube in the furnace C-stack positioned in cleanroom 2. All wafers have to be RCA cleaned before they enter the furnace, the only exceptions are wafers from PECVD2 and the LPCVD furnaces. | ||
'''The user manual, technical information and contact information can be found in LabManager:''' | '''The user manual, technical information and contact information can be found in LabManager:''' | ||
| Line 19: | Line 19: | ||
==Overview of the performance of Anneal Oxide furnace and some process related parameters== | ==Overview of the performance of Anneal Oxide furnace and some process related parameters== | ||
{| border="2" cellspacing="0" cellpadding=" | {| border="2" cellspacing="0" cellpadding="2" | ||
|- | |- | ||
!style="background:silver; color:black;" align="center"|Purpose | !style="background:silver; color:black;" align="center"|Purpose | ||
| Line 46: | Line 46: | ||
|style="background:LightGrey; color:black"|Gas flows | |style="background:LightGrey; color:black"|Gas flows | ||
|style="background:WhiteSmoke; color:black"| | |style="background:WhiteSmoke; color:black"| | ||
N<sub>2</sub>: 5 sccm | |||
O<sub>2</sub>: 5 sccm | |||
|- | |- | ||
!style="background:silver; color:black" align="center" valign="center" rowspan="2"|Substrates | !style="background:silver; color:black" align="center" valign="center" rowspan="2"|Substrates | ||
|style="background:LightGrey; color:black"|Batch size | |style="background:LightGrey; color:black"|Batch size | ||
|style="background:WhiteSmoke; color:black"| | |style="background:WhiteSmoke; color:black"| | ||
*1-30 100 mm or 150 wafers (or 50 mm wafers) per run | *1-30 100 mm or 150 mm wafers (or 50 mm wafers) per run | ||
|- | |- | ||
| style="background:LightGrey; color:black"|Substrate material allowed | | style="background:LightGrey; color:black"|Substrate material allowed | ||
| Line 59: | Line 58: | ||
*Silicon wafers (RCA cleaned) | *Silicon wafers (RCA cleaned) | ||
*Silicon wafers with layers of silicon oxide or silicon (oxy)nitride (RCA cleaned) | *Silicon wafers with layers of silicon oxide or silicon (oxy)nitride (RCA cleaned) | ||
* | *Wafers from the LPCVD furnaces | ||
* | *Wafers from PECVD2 | ||
|- | |- | ||
|} | |} | ||