Specific Process Knowledge/Thermal Process/C3 Anneal-bond furnace: Difference between revisions

From LabAdviser
Pevo (talk | contribs)
No edit summary
Pevo (talk | contribs)
Line 4: Line 4:
[[Image:C3.JPG|thumb|300x300px|C3 Anneal-bond furnace. Positioned in cleanroom 2]]
[[Image:C3.JPG|thumb|300x300px|C3 Anneal-bond furnace. Positioned in cleanroom 2]]


The Anneal-bond furnace (C3) is a Tempress horizontal furnace for oxidation and annealing of (bonded) silicon wafers.
The Anneal-bond furnace (C3) is a Tempress horizontal furnace for oxidation and annealing of new and processed (bonded) silicon wafers.


This furnace is the third furnace tube in the furnace C-stack positioned in cleanroom 2. In this furnace it is allowed to enter wafers that come directly from bonding in the EVG NIL (assuming they were very clean when entering EVG NIL and not contain any metal). Check the [http://www.labmanager.danchip.dtu.dk/view_binary.php?fileId=1250 cross contamination chart].
This furnace is the third furnace tube in the furnace C-stack positioned in cleanroom 2. In this furnace it is allowed oxidize and anneale wafers without doing a RCA clean first. Also bonded wafers comming directly from the EVG NIL (assuming they were very clean when entering EVG NIL and not contain any metal). Check the cross contamination information in LabManager can enter the furnace. Check the cross contamination information in LabManager.


'''The user manual, technical information and contact information can be found in LabManager:'''
'''The user manual, technical information and contact information can be found in LabManager:'''

Revision as of 14:11, 9 January 2014

Feedback to this page: click here

Anneal-bond furnace (C3)

C3 Anneal-bond furnace. Positioned in cleanroom 2

The Anneal-bond furnace (C3) is a Tempress horizontal furnace for oxidation and annealing of new and processed (bonded) silicon wafers.

This furnace is the third furnace tube in the furnace C-stack positioned in cleanroom 2. In this furnace it is allowed oxidize and anneale wafers without doing a RCA clean first. Also bonded wafers comming directly from the EVG NIL (assuming they were very clean when entering EVG NIL and not contain any metal). Check the cross contamination information in LabManager can enter the furnace. Check the cross contamination information in LabManager.

The user manual, technical information and contact information can be found in LabManager:

Anneal-bond Furnace (C3)

Process knowledge

Overview of the performance of Anneal Bond furnace and some process related parameters

Purpose Oxidation and annealing Oxidation:
  • Dry
  • Wet: with bubbler (water steam + N2)
Performance Film thickness
  • Dry SiO2: 50 Å to ~2000 Å (takes too long to make it thicker)
  • Wet SiO2: 50 Å to ~5 µm (takes too long to make it thicker)
Process parameter range Process Temperature
  • 800-1150 oC
Process pressure
  • 1 atm
Gas flows
  • N2:5 sccm
  • O2:5 sccm
Substrates Batch size
  • 1-30 4" wafer (or 2" wafers) per run
Substrate material allowed
  • Silicon wafers (new from the box or RCA cleaned)
  • Silicon wafers with layers of silicon oxide or silicon (oxy)nitride (RCA cleaned)
  • Quartz wafers (RCA cleaned)
  • From bonding in EVG NIL directly (assuming they fulfilled the above before entering the EVG NIL)