Specific Process Knowledge/Thermal Process/C1 Furnace Anneal-oxide: Difference between revisions

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Anneal-oxide furnace (C1)

C1 Anneal-oxide furnace. Positioned in cleanroom 2

The Anneal-oxide furnace (C1) is a Tempress horizontal furnace for oxidation and annealing of silicon wafers, e.g with layers of oxide, polysilicon or BPSG glass (from PECVD2). Both 100 mm and 150 mm wafers can be processed in the furnace.

The Anneal-oxide furnace is the upper furnace tube in the furnace C-stack positioned in cleanroom 2. All wafers have to be RCA cleaned before they enter the furnace, the only exception is wafer from PECVD2 if these have been RCA cleaned before they enter the PECVD.

The user manual, technical information and contact information can be found in LabManager:

Anneal-oxide furnace (C1)

Process knowledge

Oxidation: look at the Oxidation page
Annealing: look at the Annealing page

Overview of the performance of Anneal Oxide furnace and some process related parameters

Purpose	Oxidation and annealing	Oxidation: Dry Wet: with bubbler (water steam + N₂)
Performance	Film thickness	Dry SiO₂: 50Å to ~2000Å (it takes too long to grow a thicker oxide) Wet SiO₂: 50Å to ~5µm (it takes too long to grow a thicker oxide)
Process parameter range	Process Temperature	800-1150 ^oC
	Process pressure	1 atm
	Gas flows	Annealing: N₂: 5 sccm Dry oxidation: O₂: 5 sccm Wet oxidation: N₂: 5 sccm
Substrates	Batch size	1-30 100 mm or 150 wafers (or 50 mm wafers) per run
Substrates	Substrate material allowed	Silicon wafers (RCA cleaned) Silicon wafers with layers of silicon oxide or silicon (oxy)nitride (RCA cleaned) Quartz wafers (RCA cleaned) From PECVD2 directly (wafer have to be RCA cleaned before entering PECVD2)

@@ Line 44: / Line 44: @@
 |style="background:LightGrey; color:black"|Gas flows
 |style="background:WhiteSmoke; color:black"|
-*Annealing: N<sub>2</sub>:5 sccm
+*Annealing: N<sub>2</sub>: 5 sccm
-*Dry oxidation: O<sub>2</sub>:5 sccm
+*Dry oxidation: O<sub>2</sub>: 5 sccm
-*Wet oxidation: N<sub>2</sub>:5 sccm
+*Wet oxidation: N<sub>2</sub>: 5 sccm
 |-
 !style="background:silver; color:black" align="center" valign="center" rowspan="2"|Substrates
 |style="background:LightGrey; color:black"|Batch size
 |style="background:WhiteSmoke; color:black"|
-*1-30 4" and 6" wafer (or 2" wafers) per run
+*1-30 100 mm or 150 wafers (or 50 mm wafers) per run
 |-
 | style="background:LightGrey; color:black"|Substrate material allowed
@@ Line 58: / Line 58: @@
 *Silicon wafers with layers of silicon oxide or silicon (oxy)nitride (RCA cleaned)
 *Quartz wafers (RCA cleaned)
-*From PECVD1 directly (assuming they fulfilled the above before entering the PECVD1)
+*From PECVD2 directly (wafer have to be RCA cleaned before entering PECVD2)
 |-
 |}