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| In the case of the silicon etching on the ASE, an etch phase with SF<sub>6</sub> and O<sub>2</sub> alternates with a passivation phase with C<sub>4</sub>F<sub>8</sub>. | | In the case of the silicon etching on the ASE, an etch phase with SF<sub>6</sub> and O<sub>2</sub> alternates with a passivation phase with C<sub>4</sub>F<sub>8</sub>. |
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| === The two standard silicon etch recipes ===
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| Two recipes have been optimized for the ASE. Their specification is on a 10 % etch load wafer with trenches.
| | ==A rough overview of the performance of the RIE´s and some process related parameters== |
| * '''Shallolr''': The shallow etch process will etch a 2 <math>\mu</math>m opening down to make a 20 <math>\mu</math>m trench.
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| * '''Deepetch''': The deep etch process will etch a 50 <math>\mu</math>m opening down to make a 300 <math>\mu</math>m trench.
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| The standardization procedure on the ASE covers these two etches.
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| == Recipes on the ASE ==
| | {| border="2" cellspacing="0" cellpadding="10" |
| | |
| === Shallolr ===
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| | |
| The shallolr recipe is designed to etch features (with sizes above 1 <math>\mu</math>m) in silicon down to a depth that ranges from a few microns to some 50 microns. (If you need to etch deeper use Deepetch or more shallow, see Nanoetches.) It is specified to etch a 2 <math>\mu</math>m wide trench down to a depth of 20 <math>\mu</math>m on a wafer that has a global/local etch opening density of 10%.
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| The recipe is given below.
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| | |
| {| border="2" cellpadding="2" cellspacing="1" | |
| |+ The shallolr recipe
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| |-
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| ! colspan="2" align="center"| Common parameters
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| ! colspan="3" align="center"| Multiplexed parameters
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| |-
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| ! Parameter
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| ! Setting
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| ! Parameter
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| ! Etch
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| ! Passivation
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| |-
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| ! Temperature
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| | 10<sup>o</sup>C
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| ! SF<sub>6</sub> Flow
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| | 260 sccm
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| | 0 sccm
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| |-
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| ! No. of cycles
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| | 31
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| ! O<sub>2</sub> Flow
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| | 26 sccm
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| | 0 sccm
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| |-
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| ! Process time
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| | 5:56 mins
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| ! C<sub>4</sub>F<sub>4</sub> Flow
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| | 0 sccm
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| | 120 sccm
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| |-
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| ! APC mode
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| | manual
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| ! RF coil
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| | 2800 W
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| | 1000 W
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| |-
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| ! APC setting
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| | 86.8 %
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| ! RF Platen
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| | 16 W
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| | 0 W
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| |-
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| !
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| ! Cycle time
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| | 6.5 s
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| | 5 s
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| |}
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| The process runs for 31 cycles (5:56 mins). The fact that it's Bosch process is clear from the scallops on the sidewalls - one should be able to count 31 of them.
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| <gallery caption="Standardization images of the shallolr recipe" widths="300px" heights="300px" perrow="2">
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| Image:jmlshal070921 pos1 2mu_09.jpg|The profile of a 2 <math>\mu</math>m trench
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| image:jmlshal070921 pos1 50mu_08.jpg|The profile of a 50 <math>\mu</math>m trench
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| </gallery>
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| The process is designed to reach 20 <math>\mu</math>m down in a 2 <math>\mu</math>m trench but as is clear from the image of the corresponding 50 <math>\mu</math>m trench, this one is etched deeper. The reason is the so called Aspect Ratio Dependent Etching or ARDE: See below.
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| | |
| === Deepetch ===
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| The deepetch recipe is designed to etch features (with sizes 2 <math>\mu</math>m) in silicon down to a depth that ranges from some 50 microns to hundreds of microns. (If you need to etch less, use shallow or Nanoetches.) It is specified to etch a 50 <math>\mu</math>m wide trench down to a depth of 300 <math>\mu</math>m on a wafer that has a global/local etch density of 10%.
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| The recipe is given below.
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| | |
| {| border="2" cellpadding="2" cellspacing="1"
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| |+ The deepetch recipe
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| |-
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| ! colspan="2" align="center"| Common parameters
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| ! colspan="3" align="center"| Multiplexed parameters
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| |- | | |- |
| ! Parameter | | !style="background:silver; color:black;" align="left"|Purpose |
| ! Setting
| | |style="background:LightGrey; color:black"|Dry etch of ||style="background:WhiteSmoke; color:black"| |
| ! Parameter
| | *Silicon |
| ! Etch
| | *Silicon oxide |
| ! Passivation
| | *Silicon (oxy)nitride |
| |- | | |- |
| ! Temperature | | !style="background:silver; color:black" align="left"|Performance |
| | 20<sup>o</sup>C | | |style="background:LightGrey; color:black"|Etch rates||style="background:WhiteSmoke; color:black"| |
| ! SF<sub>6</sub> Flow
| | *Silicon: ~0.04-0.8 µm/min |
| | 230 sccm
| | *Silicon oxide:~0.02-0.15 µm/min |
| | 0 sccm
| | *Silicon (oxy)nitride:~0.02-? µm/min |
| |- | | |- |
| ! No. of cycles
| | |style="background:silver; color:black" |.||style="background:LightGrey; color:black"|Anisotropy||style="background:WhiteSmoke; color:black"| |
| | 250 | | *Can vary from isotropic to anisotropic with vertical sidewalls and on to a physical etch were the sidewalls are angled but without etching under the mask. |
| ! O<sub>2</sub> Flow
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| | 23 sccm | |
| | 0 sccm
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| |- | | |- |
| ! Process time | | !style="background:silver; color:black" align="left"|Process parameter range |
| | 54:10 mins | | |style="background:LightGrey; color:black"|Process pressure||style="background:WhiteSmoke; color:black"| |
| ! C<sub>4</sub>F<sub>4</sub> Flow
| | *~20-200 mTorr |
| | 0 sccm | |
| | 120 sccm
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| |- | | |- |
| ! APC mode
| | |style="background:silver; color:black"|.||style="background:LightGrey; color:black"|Gas flows |
| | manual | | |style="background:WhiteSmoke; color:black"| |
| ! RF coil
| | *SF<math>_6</math>: 0-130 sccm |
| | 2800 W
| | *O<math>_2</math>: 0-100 sccm |
| | 1000 W
| | *CHF<math>_3</math>: 0-100 sccm |
| | *CF<math>_4</math>: 0-84 sccm |
| | *H<math>_2</math>: ?sccm |
| | *Ar: 0-145 sccm |
| | *N<math>_2</math>: 0-100 sccm |
| | *C<math>_2</math>F<math>_6</math>: 0-24 sccm |
| |- | | |- |
| ! APC setting | | !style="background:silver; color:black" align="left"|Substrates |
| | 87.7 % | | |style="background:LightGrey; color:black"|Batch size |
| ! RF Platen
| | |style="background:WhiteSmoke; color:black"| |
| | 19 W
| | *1 4" wafer per run |
| | 0 W
| | *1 2" wafer per run |
| | *Or several smaller pieces |
| |- | | |- |
| !
| | |style="background:silver; color:black"|.|| style="background:LightGrey; color:black"|Substrate material allowed |
| | | | |style="background:WhiteSmoke; color:black"| |
| ! Cycle time
| | *Silicon wafers |
| | 8 s | | **with layers of silicon oxide or silicon (oxy)nitride |
| | 5 s | | *Quartz wafers |
| | |- |
| | |style="background:silver; color:black"|.|| style="background:LightGrey; color:black"|Possible masking material |
| | |style="background:WhiteSmoke; color:black"| |
| | *Photoresist/e-beam resist |
| | *Silicon/PolySi |
| | *Silicon oxide or silicon (oxy)nitride |
| | *Aluminium |
| | *Other metals if the coverage is <5% of the wafer area (ONLY PECVD3!) |
| | |- |
| |} | | |} |
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| <gallery caption="Standardization images of the deepetch recipe" widths="300px" heights="300px" perrow="2">
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| Image:jmldeep071101 pos1 2mu_010.jpg|The profile of a 2 <math>\mu</math>m trench
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| image:jmldeep071101 pos5 50mu_013.jpg|The profile of a 50 <math>\mu</math>m trench
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| </gallery>
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| As is clear from the two images ARDE also plays a role in this case: The 2 <math>\mu</math>m trench (widened to about 5-6 <math>\mu</math>m because of undercut/underetching) is only etched 150 <math>\mu</math>m.
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| == Standardization procedure on the ASE ==
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