In the case of the silicon etching on the ASE, an etch phase with SF<sub>6</sub> and O<sub>2</sub> alternates with a passivation phase with C<sub>4</sub>F<sub>8</sub>.
In the case of the silicon etching on the ASE, an etch phase with SF<sub>6</sub> and O<sub>2</sub> alternates with a passivation phase with C<sub>4</sub>F<sub>8</sub>.
=== The two standard silicon etch recipes ===
Two recipes have been optimized for the ASE. Their specification is on a 10 % etch load wafer with trenches.
==A rough overview of the performance of the RIE´s and some process related parameters==
* '''Shallolr''': The shallow etch process will etch a 2 <math>\mu</math>m opening down to make a 20 <math>\mu</math>m trench.
* '''Deepetch''': The deep etch process will etch a 50 <math>\mu</math>m opening down to make a 300 <math>\mu</math>m trench.
The standardization procedure on the ASE covers these two etches.
== Recipes on the ASE ==
{| border="2" cellspacing="0" cellpadding="10"
=== Shallolr ===
The shallolr recipe is designed to etch features (with sizes above 1 <math>\mu</math>m) in silicon down to a depth that ranges from a few microns to some 50 microns. (If you need to etch deeper use Deepetch or more shallow, see Nanoetches.) It is specified to etch a 2 <math>\mu</math>m wide trench down to a depth of 20 <math>\mu</math>m on a wafer that has a global/local etch opening density of 10%.
The recipe is given below.
{| border="2" cellpadding="2" cellspacing="1"
|+ The shallolr recipe
|-
! colspan="2" align="center"| Common parameters
! colspan="3" align="center"| Multiplexed parameters
|-
! Parameter
! Setting
! Parameter
! Etch
! Passivation
|-
! Temperature
| 10<sup>o</sup>C
! SF<sub>6</sub> Flow
| 260 sccm
| 0 sccm
|-
! No. of cycles
| 31
! O<sub>2</sub> Flow
| 26 sccm
| 0 sccm
|-
! Process time
| 5:56 mins
! C<sub>4</sub>F<sub>4</sub> Flow
| 0 sccm
| 120 sccm
|-
! APC mode
| manual
! RF coil
| 2800 W
| 1000 W
|-
! APC setting
| 86.8 %
! RF Platen
| 16 W
| 0 W
|-
!
|
! Cycle time
| 6.5 s
| 5 s
|}
The process runs for 31 cycles (5:56 mins). The fact that it's Bosch process is clear from the scallops on the sidewalls - one should be able to count 31 of them.
<gallery caption="Standardization images of the shallolr recipe" widths="300px" heights="300px" perrow="2">
Image:jmlshal070921 pos1 2mu_09.jpg|The profile of a 2 <math>\mu</math>m trench
image:jmlshal070921 pos1 50mu_08.jpg|The profile of a 50 <math>\mu</math>m trench
</gallery>
The process is designed to reach 20 <math>\mu</math>m down in a 2 <math>\mu</math>m trench but as is clear from the image of the corresponding 50 <math>\mu</math>m trench, this one is etched deeper. The reason is the so called Aspect Ratio Dependent Etching or ARDE: See below.
=== Deepetch ===
The deepetch recipe is designed to etch features (with sizes 2 <math>\mu</math>m) in silicon down to a depth that ranges from some 50 microns to hundreds of microns. (If you need to etch less, use shallow or Nanoetches.) It is specified to etch a 50 <math>\mu</math>m wide trench down to a depth of 300 <math>\mu</math>m on a wafer that has a global/local etch density of 10%.
The recipe is given below.
{| border="2" cellpadding="2" cellspacing="1"
|+ The deepetch recipe
|-
! colspan="2" align="center"| Common parameters
! colspan="3" align="center"| Multiplexed parameters
*Can vary from isotropic to anisotropic with vertical sidewalls and on to a physical etch were the sidewalls are angled but without etching under the mask.
! O<sub>2</sub> Flow
| 23 sccm
| 0 sccm
|-
|-
! Process time
!style="background:silver; color:black" align="left"|Process parameter range
|style="background:silver; color:black"|.|| style="background:LightGrey; color:black"|Substrate material allowed
|
|style="background:WhiteSmoke; color:black"|
! Cycle time
*Silicon wafers
| 8 s
**with layers of silicon oxide or silicon (oxy)nitride
| 5 s
*Quartz wafers
|-
|style="background:silver; color:black"|.|| style="background:LightGrey; color:black"|Possible masking material
|style="background:WhiteSmoke; color:black"|
*Photoresist/e-beam resist
*Silicon/PolySi
*Silicon oxide or silicon (oxy)nitride
*Aluminium
*Other metals if the coverage is <5% of the wafer area (ONLY PECVD3!)
|-
|}
|}
<gallery caption="Standardization images of the deepetch recipe" widths="300px" heights="300px" perrow="2">
Image:jmldeep071101 pos1 2mu_010.jpg|The profile of a 2 <math>\mu</math>m trench
image:jmldeep071101 pos5 50mu_013.jpg|The profile of a 50 <math>\mu</math>m trench
</gallery>
As is clear from the two images ARDE also plays a role in this case: The 2 <math>\mu</math>m trench (widened to about 5-6 <math>\mu</math>m because of undercut/underetching) is only etched 150 <math>\mu</math>m.
== Standardization procedure on the ASE ==
Revision as of 15:54, 19 December 2007
The ASE
The ICP-DRIE tool at Danchip: STS ASE - positioned in cleanroom2
The ICP-DRIE (Inductively Coupled Plasma - Deep Reactive Ion Etcher) tool at Danchip is manufactured by STS and is called the ASE (Advanced Silicon Etcher). The main purpose of the ASE is etching of silicon using Bosch process.
The Bosch process: Etching of silicon
The Bosch process uses alternation between an etch cycle and a passivation cycle. Introducing a passivation step in an etch process is very beneficial for the control of the angle of the sidewalls in the etch process because it allows us to cover them with a protective layer that suppresses the isotropic etching. Combined with the high plasma density in the ICP chamber, the excellent sidewall control enables us to etch high aspect ratio structures in silicon with very high etch rates.
In the case of the silicon etching on the ASE, an etch phase with SF6 and O2 alternates with a passivation phase with C4F8.
A rough overview of the performance of the RIE´s and some process related parameters
Purpose
Dry etch of
Silicon
Silicon oxide
Silicon (oxy)nitride
Performance
Etch rates
Silicon: ~0.04-0.8 µm/min
Silicon oxide:~0.02-0.15 µm/min
Silicon (oxy)nitride:~0.02-? µm/min
.
Anisotropy
Can vary from isotropic to anisotropic with vertical sidewalls and on to a physical etch were the sidewalls are angled but without etching under the mask.
Process parameter range
Process pressure
~20-200 mTorr
.
Gas flows
SF: 0-130 sccm
O: 0-100 sccm
CHF: 0-100 sccm
CF: 0-84 sccm
H: ?sccm
Ar: 0-145 sccm
N: 0-100 sccm
CF: 0-24 sccm
Substrates
Batch size
1 4" wafer per run
1 2" wafer per run
Or several smaller pieces
.
Substrate material allowed
Silicon wafers
with layers of silicon oxide or silicon (oxy)nitride
Quartz wafers
.
Possible masking material
Photoresist/e-beam resist
Silicon/PolySi
Silicon oxide or silicon (oxy)nitride
Aluminium
Other metals if the coverage is <5% of the wafer area (ONLY PECVD3!)
