Specific Process Knowledge/Etch/ASE (Advanced Silicon Etch): Difference between revisions
No edit summary |
No edit summary |
||
Line 18: | Line 18: | ||
== Recipes on the ASE == | == Recipes on the ASE == | ||
=== | === Shallolr === | ||
The shallolr recipe is designed to etch features (with sizes above 1 <math>\mu</math>m) in silicon down to a depth that ranges from a few microns to some 50 microns. If you need to etch deeper use Deepetch or more shallow, see Nanoetches. | |||
The recipe is given below. | |||
{| border="2" cellpadding="2" cellspacing="1" align="left" | {| border="2" cellpadding="2" cellspacing="1" align="left" | ||
|+ The shallolr recipe | |+ The shallolr recipe | ||
Line 70: | Line 70: | ||
| 5 s | | 5 s | ||
|} | |} | ||
[[image:jmlshal070921 pos1 2mu_09.jpg|370x370px|thumb|right|Standardization image of the profile of a 2 <math>\mu</math>m trench]] | |||
Revision as of 14:44, 11 December 2007
The ASE
The ICP-DRIE (Inductively Coupled Plasma - Deep Reactive Ion Etcher) tool at Danchip is manufactured by STS and is called the ASE (Advanced Silicon Etcher). The main purpose of the ASE is etching of silicon using Bosch process.
The Bosch process: Etching of silicon
The Bosch process uses alternation between an etch cycle and a passivation cycle. Introducing a passivation step in an etch process is very beneficial for the control of the angle of the sidewalls in the etch process because it allows us to cover them with a protective layer that suppresses the isotropic etching. Combined with the high plasma density in the ICP chamber, the excellent sidewall control enables us to etch high aspect ratio structures in silicon with very high etch rates.
In the case of the silicon etching on the ASE, an etch phase with SF6 and O2 alternates with a passivation phase with C4F8.
The two standard silicon etch recipes
Two recipes have been optimized for the ASE. Their specification is on a 10 % etch load wafer with trenches.
- Shallolr: The shallow etch process will etch a 2 m opening down to make a 20 m trench.
- Deepetch: The deep etch process will etch a 50 m opening down to make a 300 m trench.
The standardization procedure on the ASE covers these two etches.
Recipes on the ASE
Shallolr
The shallolr recipe is designed to etch features (with sizes above 1 m) in silicon down to a depth that ranges from a few microns to some 50 microns. If you need to etch deeper use Deepetch or more shallow, see Nanoetches. The recipe is given below.
Common parameters | Multiplexed parameters | |||
---|---|---|---|---|
Parameter | Setting | Parameter | Etch | Passivation |
Temperature | 10oC | SF6 Flow | 260 sccm | 0 sccm |
No. of cycles | 31 | O2 Flow | 26 sccm | 0 sccm |
Process time | 5:56 mins | C4F4 Flow | 0 sccm | 120 sccm |
APC mode | manual | RF coil | 2800 W | 1000 W |
APC setting | 86.8 % | RF Platen | 16 W | 0 W |
Cycle time | 6.5 s | 5 s |
Deepetch
Common parameters | Multiplexed parameters | |||
---|---|---|---|---|
Parameter | Setting | Parameter | Etch | Passivation |
Temperature | 20oC | SF6 Flow | 230 sccm | 0 sccm |
No. of cycles | 250 | O2 Flow | 23 sccm | 0 sccm |
Process time | 54:10 mins | C4F4 Flow | 0 sccm | 120 sccm |
APC mode | manual | RF coil | 2800 W | 1000 W |
APC setting | 87.7 % | RF Platen | 19 W | 0 W |
Cycle time | 8 s | 5 s |