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| | | ==Using LPCVD TEOS as a masking material for KOH etching== |
| | | It is possible to use TEOS as a masking layer in KOH etch however it is not as suitable as Silicon nitride for deep KOH etching. However for shallower etches it can be used. In comparison to silicon nitride TEOS has the advantage that it does not have the same pinhole problems. |
| ==Using LPCVD silicon nitride as a masking material for KOH etching== | |
| At Danchip stoichiometric silicon nitride is mainly used as masking material for potassium hydroxide (KOH) etching. The etch rate of the nitride in 80 <sup>o</sup>C KOH is expected to be less than 1 Å/min.
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| There are regularly users having problems with pinholes in the silicon nitride after KOH etching. It is not always clear what the reasons are, but we suspect problems can arise due to
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| *too many or too large particles in the nitride.
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| *too rough handling of the wafers after the nitride deposition.
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| *too much stress between the nitride and the underlying layer.
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| ===Our recommendations to try and avoid pinhole problems are:===
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| '''To avoid too many or too large particles in the nitride'''<br\>
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| *Use the new nitride furnace, if you have to deposit stoichiometric nitride. In order to avoid problems with particles it is not allowed to deposit low stress nitride in this furnace, and the particles level is therefore low compared to the older nitride furnace
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| *Before running a process keep in close contact with the Danchip staff (especially the process specialist on the furnace) or take a look at the logbook to make sure that the nitride furnace is expected to be in a good state.
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| '''To avoid too rough handling of the wafers after the nitride deposition'''<br\>
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| *After the deposition handle the wafers with a clean glove on the edge of the wafers (no tweezers).
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| *Be careful not to scratch wafers with nitride (e.g. up against each other or on the spinner or the aligner).
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| *If you have nitride on the back side of a wafer while aligning, consider if you can protect it with e.g. a photoresist layer before loading it onto the aligner. Or use a non-vacuum aligner chuck with a big hole in the middle, so that the wafer is only laying on the edge. Avoid hard contact in the aligner if possible.
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| '''To avoid too much stress between the nitride and the underlying layer'''<br\>
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| *It is recommended to have a of silicon oxide layer between the silicon substrate and the nitride layer to reduce the stress level between the layers. The silicon nitride is then expected to have less tendency to break.
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| for sjov
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| <math>
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| \mathcal{V}^\prime=-\sqrt{rcs}A\cosh(\sqrt{rcs}(L-x))-\sqrt{rcs}B\sinh(\sqrt{rcs}(L-x))
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| </math>
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| <math> Z=\frac{\mathcal{V}(0)}{\mathcal{I}(0)}=rL\frac{B\cosh(\sqrt{rcs}L)}{\sqrt{rcs}LB\sinh(\sqrt{rcs}L)} </math>
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| [[image:RIE1_Si_Angle_O2_CHF3.jpg|300x300px|thumb|right|Angle of sidewall on 1.5 µm trenches - independent on pressure within the given pressure range]]
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| <math>
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| \includegraphics[width=0.5\textwidth]{RIE1_Si_Angle_O2_CHF3.jpg}
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| \caption{The simplified model, which can be used in stead of the
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| one in figure. In this representation is
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| the total resistance in the entire transmission lines, not just
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| between the capacitors.}
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| </math>
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