LabAdviser/Technology Research/Technology Development of 3D Silicon Plasma Etching process for Novel Devices and Applications: Difference between revisions
Appearance
| Line 49: | Line 49: | ||
:Microelectronic Engineering (2018) [https://doi.org/10.1016/j.mee.2018.02.023 DOI] | :Microelectronic Engineering (2018) [https://doi.org/10.1016/j.mee.2018.02.023 DOI] | ||
==Conference contributions== | |||
*;'''RIE-lag “Correction” and Infinite Etching Selectivity with Conventional Photoresist in a Bosch Process''' | |||
:<u>Chang, B.</u>, Leussink, P., Jensen, F., Hübner, J. and Jansen, H. | |||
:Poster presentation at 43rd International conference on Micro and Nano Engineering, Braga, Portugal (2017) | |||
*;'''Three dimensional engineering of silicon micro- and nanostructures''' | |||
:<u>Chang, B.</u>, Jensen, F., Hübner, J. and Jansen, H. | |||
:Oral presentation at 44rd International conference on Micro and Nano Engineering, Copenhagen, Denmark (2018) | |||