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| *[[Specific Process Knowledge/Etch/DRIE-Pegasus/processD|Process D (Micro stamp): ]] | | *[[Specific Process Knowledge/Etch/DRIE-Pegasus/processD|Process D (Micro stamp): ]] |
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| | *[[Specific Process Knowledge/Etch/DRIE-Pegasus/SOIetch|SOI etch]] |
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| === Process A ===
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| Process A is labelled ''Large trench (80μm wide) 150μm depth''. In the acceptance test the process was run on a 150 mm SPTS wafer with 12-13 % etch load.
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| [[Specific Process Knowledge/Etch/DRIE-Pegasus/processA|Process A: Recipe, specifications and results]]
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| === Process B ===
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| Process A is labelled ''Via (30μm diameter) 100μm depth''. In the acceptance test the process was run on a 150 mm SPTS wafer with 12-13 % etch load.
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| [[Specific Process Knowledge/Etch/DRIE-Pegasus/processB|Process B: Recipe, specifications and results]]
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| === Process C ===
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| Process A is labelled ''Nano silicon etch''. In the acceptance test the process was run on a 100 mm Danchip wafer with a test pattern of a series of lines and dots with sizes ranging from 30 nm to 300 nm. The etch load was extremely high, approaching 100 %.
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| [[Specific Process Knowledge/Etch/DRIE-Pegasus/processC|Process C: Recipe, specifications and results]]
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| === Process D ===
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| Process D is labelled ''Micro stamp etch''.
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| In the acceptance test the process was run on a 100 mm wafer with 50 % etch load.
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| [[Specific Process Knowledge/Etch/DRIE-Pegasus/processD|Process D: Recipe, specifications and results]]
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| === SOI etch ===
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| The SOI etch uses the Low frequency (LF) platen generator to minimize the notching at buried stop layers such as the BOX layer in a SOI wafer. | | The SOI etch uses the Low frequency (LF) platen generator to minimize the notching at buried stop layers such as the BOX layer in a SOI wafer. |
