Specific Process Knowledge/Lithography/EBeamLithography/Nanobook: Difference between revisions
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For this exposure we coated a 100 mm Si wafer with 70 nm ZEP 520A resist. To hit the relatively small feature size it is essential to work with a thin resist layer. | For this exposure we coated a 100 mm Si wafer with 70 nm ZEP 520A resist. To hit the relatively small feature size it is essential to work with a thin resist layer. | ||
The exposure was done on our state of the art JEOL 9500 FSZ exposure system. If you are interested in seeing the system in operation consider this video on our Youtube channel. Exposure was done at a low beam current of only 0.22 nA and a voltage of 100 keV. The DTU logo on the chip was however exposed at a much higher beam current. | The exposure was done on our state of the art JEOL 9500 FSZ exposure system. If you are interested in seeing the system in operation consider [https://youtu.be/2bFUO201DS4?si=1GJKJLrZCRnwPmRq this video on our Youtube channel]. Exposure was done at a low beam current of only 0.22 nA and a voltage of 100 keV. The DTU logo on the chip was however exposed at a much higher beam current. | ||
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