Specific Process Knowledge/Etch/DRIE-Pegasus

The SPTS Pegasus in the Danchip cleanroom

The DRIE Pegasus at Danchip

The DRIE Pegasus is a state-of-art silicon dry etcher. It offers outstanding performance in terms of etch rate, uniformity etc. This page will provide some clues.

The Bosch process in the DRIE-Pegasus

The DRIE-Pegasus takes the well established Bosch process known from the ASE a significant step further. In the ASE the Bosch process has two cycles, etch and passivation. During each cycle the process parameters are kept constant (This is, at least, that is the intention - the reality is that the ideal square function is rarely achieved during process parameter changes).

• In the passivation cycle, a C₄F₈ plasma is formed using the RF coil power only and a teflon-like coating is created on all surfaces thus protecting the sidewalls in the subsequent etch cycle.
• In the etch cycle
  • the ion bombardment driven by the platen power first removes the passivation layer on the surfaces directly exposed to the ions (i.e. horizontal surfaces)
  • then as the bottom of the structures are opened the etch of silicon itself starts.

The etch cycle may be split into three parts, Boost, Delay and Main, where process parameters such as pressure, gas flows or RF powers have different values.

Here, it is clear that one can distinguish two phases of the etch cycle; one where the ion bombardment removes the polymer and one where the actual etching of silicon takes place. Considering what process conditions are favorable we realize that

1. the ion bombardment requires a low pressure in order for the ions to have a long mean free path and hence good directionality. Also, a high platen power is required to drive the ion bombardment.
2. a higher pressure during the etch increases the density of reactive species and hence the etch rate. Since a high platen power is no longer necessary to drive the ion bombardement, lowering it will reduce the impact on the masking material thus improving the selectivity.

These conflicting demands are the same on the ASE. However, with hardware improvements on the DRIE-Pegasus such as

• fast response digtal MFC's mounted on top of the process chamber itself to shorten the gas line
• fast APC valve
• fast RF power supply

the etch and deposition cycles may be split into three separate phases, called Delay, Boost and Main. Following the arguments from above, the third phase (Delay) may be thought of as a short delay that ensures a very low pressure (and thus extremely good ion directionality) before the ion bombardment. The standard etches on the Pegasus only make use of up to two phases.

Processing options on the Pegasus

The Pegasus has a lot of advanced processing options.

1. Multiplexing: As described above, the multiplexed Bosch process may have the etch or passivation cycle each split into three separate phases: Delay, Boost and Main.
2. Ramping:Using the ramp option one can change process parameters linearly over the course of each processing step.
3. Process steps: Stich any number of processing steps with different parameters to make one continuous process.
4. Hardware: The Pegasus has several hardware settings:
   1. Spacers : The distance to the plasma source may be changed by using different spacers.
   2. Baffle and funnel: The funnel inside the chamber helps to focus the plasma/ions towards the electrode. They may be taken out but don't expect this option to be part of the parameters that you can change in your experiments.

This gives an infinite process parameter space....

The standard processes: Process A, B, C and D

How to read the SPTS notation on process recipes

Two words about the SPTS short notation on process recipes: When, take for instance the etch cycle from step 1 in Process A below, it is written Platen power 120 >> 140 (1.5s) 45 it is to be interpreted as:

1. In the first 1.5 seconds of the every cycle the platen power has a value that is ramped (indicated by >>) from 120 W initially to 150 W in the end
2. During the reminder of the cycle the platen power is kept constant at 45 W.

Process A

Process A is labelled Large trench (80μm wide) 150μm depth. In the acceptance test the process was run on a 150 mm SPTS wafer with 12-13 % etch load.

Process A: Recipe, specifications and results

Process B

Process A is labelled Via (30μm diameter) 100μm depth. In the acceptance test the process was run on a 150 mm SPTS wafer with 12-13 % etch load.

Process B: Recipe, specifications and results

Process C

Process A is labelled Nano silicon etch. In the acceptance test the process was run on a 100 mm Danchip wafer with a test pattern of a series of lines and dots with sizes ranging from 30 nm to 300 nm. The etch load was extremely high, approaching 100 %.

Process C: Recipe, specifications and results

Process D

Process D is labelled Micro stamp silicon etch. In the acceptance test the process was run on a 150 mm wafer with 12-13 % etch load.

Process D: Recipe, specifications and results

Nanoetching

Nanoetch (Under construction)

User manuals

• The Danchip user manual from LabManager is found >Here<.
• The user manual provided by SPTS can be found here >HERE<

Hardware information

Hardware Information - Overview.

Hardware Information - Detailed.

The Advantages the Pegasus has over existing Si etchers.

Robot Handling System Information .

Process applications

The acceptance test for the DRIE-Pegasus system, April 2010.

MEMS in Aerospace.

Bio Medical.

MEMS in Energy.

Nanotechnology.

Packaging Applications.

General Applications.

Further info:

FAQ (Under construction)

1. Presentation
2. The Bosch process
3. The standard etches
4. Additional etches including nanoetch
5. Processing challenges such as bonded wafers
6. SPTS documents