Specific Process Knowledge/Etch/DRIE-Pegasus/Pegasus-4/SiO2 Etch: Difference between revisions
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Using the electromagnetic coil on the recipe SiO2_res_10 gave higher etch rate on this chip that was placed in the center of a 6" wafer. The Etch profile is more angles. | |||
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Revision as of 08:18, 11 September 2023
SiO2 Etch using resist as masking material
Unless otherwise stated, all content in this section was done by Berit Herstrøm, DTU Nanolab
I have do some development of a SiO2 etch with resist as masking material. I have found this fairly good recipe. For now it is the standard SiO2 etch recipes but I might change the "Standard recipe" a a later time if I find a better one. If you need to etch deeper than 1 micrometer then I advise you to split the etch in several runs with O2 cleans in between (3min TDESC Clean) or else it seems like the the etch rate is going down over time.
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0.4µ/0.2µ
Bad lithography -
0.5/0.25µ
Etch depth: 652 nm
Resist left: 456 nm -
1µ/0.5µ:
Etch depth: 855 nm
Resist left: 487 nm -
2µ/1µ:
Etch depth: 952 nm
Resist left: 487 nm -
4µ/2µ:
Etch depth: 1106 nm
Resist left: 487 nm -
0.8µ/0.2µ
Etch depth: 867 nm
Resist left: 426 nm -
1.0µ/0.25µ:
Etch depth: 893 nm
Resist left: 460 nm -
4µ/1µ:
Etch depth: 1033 nm
Resist left: 473 nm
Uniformity results with SiO2_res_10
Using the electromagnetic coil on the recipe SiO2_res_10 gave higher etch rate on this chip that was placed in the center of a 6" wafer. The Etch profile is more angles.
SiO2 Etch using aSi as masking material
Unless otherwise stated, all content in this section was done by Berit Herstrøm, DTU Nanolab
I am now starting up development of SiO2 etch using aSi as masking material.
The samples I use are:
- 6" Si afters with oxide (2µm),
- aSi (~300nm),
- Neg. DUV reist (~60nm barc, ~350 nm resist)
- Reticle: Danchip/Triple-D
- Dose 230 J/m2
First I need to make sure that the resist work for pattering the aSi layer is good. If the resist is not good the final etch will also not be good.
DUV optimization
Dose test with the doses (J/m2): 200, 210, 220, 230, 240, 250, 270, 280 The aim was to get good line for 400nm pitch/200nm lines
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200 J/m2 400nm/268nm
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210 J/m2 400nm/239nm
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220 J/m2 400nm/208nm
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230 J/m2 400nm/209nm
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240 J/m2 400nm/215nm
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250 J/m2 400nm/207nm
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260 J/m2 400nm/188nm
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270 J/m2 400nm/155nm
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280 J/m2 400nm/0nm
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210 J/m2 1000nm/581nm
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230 J/m2 1000nm/517nm
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240 J/m2 1000nm/518nm
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250 J/m2 1000nm/510nm
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260 J/m2 1000nm/493nm
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270 J/m2 1000nm/494nm
Testing with electromagnetic coils
Unless otherwise stated, all content in this section was done by Berit Herstrøm, DTU Nanolab
When testing with decreased platen power on the SiO2_10 standard recipe the uniformity got very bad. I then tested with the electromagnetics coil to see if that could affect the uniformity. There is an outer coil that can be varied between 0 A and 10 A and an inner coil that can be varied between 0 A and 30 A. The first tests were done on Si/SiO2(1µm) without pattern and measured on the ellipsometer.
Parameter | Recipe name: no 10 with lower platen power |
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Coil Power [W] | 2500 |
Platen Power [W] | 200 |
Platen temperature [oC] | 20 |
H2 flow [sccm] | 25.6 |
C4F8 flow [sccm] | 25.6 |
He flow [sccm] | 448.7 |
Pressure | Fully open APC valve (8-9 mTorr) |
Electromagnetic coils (EM) 'outer coil' / 'inner coil' | '0-10 A' / '0-30 A' |
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Etch time: 2 min, Average etch rate: 100.2 nm/min, range:+-55.1%
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Etch time: 2 min, Average etch rate: 100.5 nm/min, range:+-32.6%
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Etch time: 2 min, Average etch rate: 100.8 nm/min, range:+-50.8%
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Etch time: 2 min, Average etch rate: 203.8 nm/min, range:+-6.1%
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Etch time: 2 min, Average etch rate: 186.2 nm/min, range:+-3.2%
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Etch time: 6 min on patterned wafer with different measurement points, <100 nm Cr mask is still on, EM_2/30, Average etch rate: 207-223 nm/min depending on how much Cr mask is left, range:+-2.3%