Specific Process Knowledge/Lithography/EBeamLithography/JEOLAlignment: Difference between revisions

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 ==Job preparation==
-The job illustrated below writes a chip layout in a 5 x 5 matrix into a 2 x 2 matrix as illustrated in the figure. The first layer, L1, has defined global marks at P = (-30000,0) and Q = (30000,0). The local chip marks are placed at M1 = (-450,450), M2 = (450,450), M3 = (450,-450) and M4=(-450,-450). First a global alignment is called via the '''GLMDET''' command and subsequently chip alignment is called using the '''CHIPAL''' command. The mark positions are stated in the JDF file using the '''GLMPOS''' command for PQ marks and the '''M1''' to '''M4''' commands for chip marks.
+The job illustrated below writes a chip layout in a 5 x 5 matrix into a 2 x 2 matrix as illustrated in the figure. The first layer, L1, has defined global marks at P = (-30000,0) and Q = (30000,0). The local chip marks are placed at M1 = (-450,450), M2 = (450,450), M3 = (450,-450) and M4=(-450,-450). First a global alignment is called via the '''GLMDET''' command and subsequently chip alignment is called using the '''CHIPAL''' command. The mark positions are stated in the JDF file using the '''GLMPOS''' command for PQ marks and the '''M1''' to '''M4''' commands for chip marks. Remember that a V30 file is placed relative to its bounding box center coordinate and hence it might be necessary to control the bounding box extents by adding control geometry (corner marks) if the design is not symmetric around (0,0) in the chip design coordinate system.
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-===Chip alignment SDF ===
+The following SDF and JDF files will be used for the example.
 <pre>
+;SDF
 MAGAZIN	'THOPE'
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 CALPRM '6na_ap5'
 DEFMODE 2
-GLMDET S
+GLMDET A
 CHIPAL 1
 HSWITCH OFF,ON
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 END 8
 </pre>
-'''CHIPAL [mode]'''
-'''CHIPAL''' has six modes
-*0 - Cancels chip alignment
-*S - SEM mode. The user is prompted to use SEM mode to manually find M1
-*1 - One mark is used for position correction
-*4 - Four marks are used for position, rotation and gain correction
-*V1 - Virtual mode 1. A single mark position is used for height detection of the substrate, no position correction
-*V4 - Virtual mode 4. Four mark positions are used for height detection of the substrate, no position correction
-In addition to position correction mode 1 and 4 also detects substrate height. The virtual modes are only used to detect substrate height since no mark detection is done. Mode S obviously very time consuming for a high number of chips.
-If set up properly on good quality marks mode 1 or mode 4 chip alignment can usually execute in about 1-2 seconds per mark. The time estimate at compilation will account for the time spend on chip alignment at the current settings of the '''CHIPAL''' subprogram.
-===Chip alignment JDF ===
-In addition to the use of '''CHMPOS''' for chip mark position definition the example below illustrate making arrays of an array. The first array is set up as a 2x2 array assigning array '''A1'''. '''A1''' is defined below as '''1:''', since '''1''' is defined as an array it can be referenced as '''A1'''. '''A''' then defines a 5x5 array assigning pattern '''P(1)''' to each element. The chip mark position command must be used in the same array that assigns the corresponding pattern.
 <pre>
+;JDF
 JOB/W    'THOPE',4  ; 4inch wafer