Specific Process Knowledge/Lithography/EBeamLithography/JEOLPatternPreparation: Difference between revisions
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In the wafer scale layout, L1 is exposed with a set of global alignment marks (P & Q marks) in order to allow alignment of the next wafer scale layer, L2. Thus the placement of L2 is determined entirely by a single set of alignment marks. In the chip array design, in addition to the global alignment marks (P & Q marks) chip alignment marks for each instance of the chip design is also produced. Thus the placement of each instance of L2 is determined by a local mark very close to where the pattern of L2 is actually printed for increased alignment precision. | In the wafer scale layout, L1 is exposed with a set of global alignment marks (P & Q marks) in order to allow alignment of the next wafer scale layer, L2. Thus the placement of L2 is determined entirely by a single set of alignment marks. In the chip array design, in addition to the global alignment marks (P & Q marks) chip alignment marks for each instance of the chip design is also produced. Thus the placement of each instance of L2 is determined by a local mark very close to where the pattern of L2 is actually printed for increased alignment precision. | ||
Global alignment using P & Q marks is done using the SETWFR subprogram. The P & Q mark coordinates are defined in the substrate coordinate system (X,Y). For instance, on a 4" wafer it is typical to place the P and Q marks at (- | Global alignment using P & Q marks is done using the SETWFR subprogram. The P & Q mark coordinates are defined in the substrate coordinate system (X,Y). For instance, on a 4" wafer it is typical to place the P and Q marks at (-35000,0) and (35000,0), respectively. | ||
Chip marks are different however as illustrated in the right most part of the illustration below. Chip mark coordinates refer to the local chip coordinate system (X',Y'). For instance, if a chip design has a size of 800 x 800 µm it would be convenient to place chip alignment marks at M1 = (-500,500), M2 = (500,500), M3 = (500,-500) and M4 = (-500,-500). If using more than one chip mark the order must be as specified in the illustration. The JEOL system supports 1 or 4 mark chip alignment (CHIPAL 1 or CHIPAL 4). | Chip marks are different however as illustrated in the right most part of the illustration below. Chip mark coordinates refer to the local chip coordinate system (X',Y'). For instance, if a chip design has a size of 800 x 800 µm it would be convenient to place chip alignment marks at M1 = (-500,500), M2 = (500,500), M3 = (500,-500) and M4 = (-500,-500). If using more than one chip mark the order must be as specified in the illustration. The JEOL system supports 1 or 4 mark chip alignment (CHIPAL 1 or CHIPAL 4). | ||