Specific Process Knowledge/Lithography/EBeamLithography/JEOLPatternPreparation: Difference between revisions
| Line 37: | Line 37: | ||
In the wafer scale layout, L1 was exposed with a set of global alignment marks (P & Q marks) in order to align the next wafer wide layer, L2. Thus the placement of L2 is determined entirely by a single set of alignment marks. In the chip array design the first exposure of L1 also produced a set of global alignment marks (P & Q marks) but additionally produced a chip alignment mark for each instance of the chip design. Thus the placement of each instance of L2 is determined by a local mark very close to where the pattern of L2 is actually printed for increased alignment precision. | In the wafer scale layout, L1 was exposed with a set of global alignment marks (P & Q marks) in order to align the next wafer wide layer, L2. Thus the placement of L2 is determined entirely by a single set of alignment marks. In the chip array design the first exposure of L1 also produced a set of global alignment marks (P & Q marks) but additionally produced a chip alignment mark for each instance of the chip design. Thus the placement of each instance of L2 is determined by a local mark very close to where the pattern of L2 is actually printed for increased alignment precision. | ||
Global alignment using P & Q marks is done using the SETWFR subprogram. The P & Q mark coordinates are defined in the substrate coordinate system. For instance, on a 4" wafer it is typical to place the P and Q marks at (-40000,0) and (40000,0), respectively. | Global alignment using P & Q marks is done using the SETWFR subprogram. The P & Q mark coordinates are defined in the substrate coordinate system (X,Y). For instance, on a 4" wafer it is typical to place the P and Q marks at (-40000,0) and (40000,0), respectively. | ||
Chip marks are different however as illustrated in the right most part of the illustration below. Chip mark coordinates refer to the local chip coordinate system. For instance, if a chip design has a size of 800 x 800 µm it would be customary to place alignment marks at M1 = (-500,500), M2 = (500,500), M3 = (500,-500) and M4 = (-500,-500). If using more than one chip mark the order must be as specified in the illustration. | Chip marks are different however as illustrated in the right most part of the illustration below. Chip mark coordinates refer to the local chip coordinate system (X',Y'). For instance, if a chip design has a size of 800 x 800 µm it would be customary to place alignment marks at M1 = (-500,500), M2 = (500,500), M3 = (500,-500) and M4 = (-500,-500). If using more than one chip mark the order must be as specified in the illustration. | ||
{| style="border: none; border-spacing: 0; margin: 1em auto; text-align: center;" | {| style="border: none; border-spacing: 0; margin: 1em auto; text-align: center;" | ||