Specific Process Knowledge/Lithography/EBeamLithography/JEOLPatternPreparation: Difference between revisions
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=== Placement of alignment marks === | === Placement of alignment marks === | ||
Global alignment marks should be placed at the left-most and right-most part of the layout. They should however not be placed closer than 15 mm to the edge of a round wafer slot as this can interfere with height sensing of the alignment mark. If alignment marks are placed too close to the edge of a wafer slot height sensing of the marks must be disabled using the HSWITCH command. | |||
Chip marks should be placed at the corners of each chip with a gap of at least 200 µm to any important structure. Bear in mind that beam scan during alignment is a high dose exposure of the mark area and hence this resist will develop (for a positive resist). This is illustrated in the microscope images below. | |||