Specific Process Knowledge/Etch/DRIE-Pegasus: Difference between revisions

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2.2 Wafer requirements
2.2 Wafer requirements


2.3 Process parameter space
2.3 Process parameter space
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   2.4.1 Process A Large trench
   2.4.1 Process A Large trench


   2.4.1 Process B Via etch
   2.4.1 Process B Via etch
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Go to the Danchip LabAdviser page to find the most recent process development.
Go to the Danchip LabAdviser page to find the most recent process development.


6  
6 User maintenance and trouble shooting
 
6.x Pegasus acronyms


  8)  Processing guidelines and instructions
  8)  Processing guidelines and instructions

Revision as of 17:22, 7 September 2010

This page is under construction

1 SPTS Pegasus DRIE introduction


1.1 Identification of equipment


1.2 Equipment responsible


1.3 Location of equipment


1.4 Safety


1.5 Purpose

The DRIE-Pegasus etch tool is a state-of-the-art silicon etch tool. The combination of advanced hardware and software enables you to either use the optimized standard processes or to tailor etch processes for your specific needs.


1.6 Overview of equipment

Image: The load lock and MACS

Image: The source in the service area

Image: The graphical user interface


2 Technical specifications

2.1 Hardware summary

  • Endpoint detection
  • 5KW 13.56MHz RF power supply and fast acting matching unit
  • Low notching Silicon On Insulator (SOI) capability
  • MACS (Multiplex Atmospheric Cassette System)

2.2 Wafer requirements


2.3 Process parameter space

2.4 Standard processes

 2.4.1 Process A Large trench


 2.4.1 Process B Via etch
 2.4.1 Process C Microstamp

 2.4.1 Process D Nanostamp


3 Processing


3. System control

Image: Description of the GUI


3.1 Manual processing


3.2 Automatic processing


4 Recipes

5 Datalogs


5 Process development

Go to the Danchip LabAdviser page to find the most recent process development.

6 User maintenance and trouble shooting

6.x Pegasus acronyms

8)  Processing guidelines and instructions
 8.1)  Bonding to a carrier wafer
  8.1.1)  Why use carrier wafers
  8.1.2)  How to bond to a carrier wafer
  8.1.3)  Processing a bonded wafer
 8.2)  Processing wafers with metal
  8.2.1)  Rules for allowing metals in the ASE
 8.3)  Recipes
9)  Operating instructions
 9.1)  Processing procedure
 9.2)  Setting the chuck temperature
 9.3)  Loading wafers
 9.4)  Processing
 9.5)  The sequencer
 9.6)  Chamber conditioning
 9.7)  Datalogs
10)  User maintenance and trouble shooting
 10.1)  Maintenance by users
 10.2)  Trouble shooting
 10.3)  Other information
  10.3.1)  Training
  10.3.2)  Literature
  10.3.3)  ASE acronyms