Specific Process Knowledge/Etch/III-V ICP/InP-InGaAsP-InGaAs: Difference between revisions
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InP piece patterned with SiO2. The piece was etched on top of a Si wafer without bonding. The recipe "InP etch" was used. The roughness looks high in the bottom of the etched areas, especially in the large open areas. | InP piece patterned with SiO2. The piece was etched on top of a Si wafer without bonding. The recipe "InP etch" was used. The roughness looks high in the bottom of the etched areas, especially in the large open areas. | ||
<gallery caption="Result of InP etching." widths="500px" heights="400px" perrow="3"> | <gallery caption="Result of InP etching." widths="500px" heights="400px" perrow="3"> | ||
Image:S1_30dg_10.jpg|low roughness in narrow trenched | |||
Image:S1_30dg_09.jpg|low roughness in narrow trenched | Image:S1_30dg_09.jpg|low roughness in narrow trenched | ||
Image:S1_30dg_midt_14.jpg|A little higher roughnedd is larger trences | Image:S1_30dg_midt_14.jpg|A little higher roughnedd is larger trences | ||
Image:S1_30dg_midt_13.jpg|Much larger roughness in open areas | Image:S1_30dg_midt_13.jpg|Much larger roughness in open areas | ||
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Image:S1_30dg_midt_11.jpg|closed look at the large roughness in the open areas. | Image:S1_30dg_midt_11.jpg|closed look at the large roughness in the open areas. | ||
</gallery> | </gallery> | ||
===Etching of an InP piece on SiO2 carrier=== | ===Etching of an InP piece on SiO2 carrier=== | ||