Specific Process Knowledge/Etch/III-V ICP/InP-InGaAsP-InGaAs: Difference between revisions
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==InP etching June 2018== | ==InP etching June 2018== | ||
===Sample pattern before etching=== | |||
<gallery caption="Result of InP etching." widths="500px" heights="400px" perrow="3"> | |||
Image:S0_oxide_01.jpg | |||
Image:S0_oxide_02.jpg | |||
</gallery> | |||
===Etching of an InP piece on Si carrier=== | ===Etching of an InP piece on Si carrier=== | ||
InP piece patterned with SiO2. The piece was etched on top of a Si wafer without bonding. The recipe "InP etch" was used. The roughness looks high in the bottom of the etched areas, especially in the large open areas. | InP piece patterned with SiO2. The piece was etched on top of a Si wafer without bonding. The recipe "InP etch" was used. The roughness looks high in the bottom of the etched areas, especially in the large open areas. | ||
Revision as of 10:55, 20 June 2018
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InP/InGaAsP/InGaAs etch
Unselective etch for large sized features and small aspect ratios by David Larsson, DTU Photonics, 2011
| Recipe | InP Etch 1/InP Precond 1 |
| Cl2 flow | 20 sccm |
| N2 flow | 40 sccm |
| Ar flow | 10 sccm |
| Platen power | 100 W |
| Coil power | 500 W |
| Pressure | 2 mTorr |
| Platen chiller temperature | 180 oC |
| Comment | Use SiO2 carrier (not Si) (Kabi/Bghe June 2018) |
| Results (InP Etch 1) | |
| Etch rate | 500-600 nm/min |
| Sidewall angle | 86-87 o |
| Selectivity (InP:SiO2, InP:HSQ) | 50:1 |
- Result of InP etching. David Larsson, DTU Photonics, 2011
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InP etching June 2018
Sample pattern before etching
- Result of InP etching.
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-
Etching of an InP piece on Si carrier
InP piece patterned with SiO2. The piece was etched on top of a Si wafer without bonding. The recipe "InP etch" was used. The roughness looks high in the bottom of the etched areas, especially in the large open areas.
- Result of InP etching.
-
low roughness in narrow trenched -
low roughness in narrow trenched -
A little higher roughnedd is larger trences -
Much larger roughness in open areas -
Zoom in on the large roughness -
closed look at the large roughness in the open areas.
Etching of an InP piece on SiO2 carrier
InP piece patterned with SiO2. The piece was etched on top of a Si wafer coated with SiO2 without bonding. The recipe "InP etch" was used. The roughness looks low in the bottom of the etched areas, even in the large open areas.
- Result of InP etching.
-
Top view: oxide is gone on the narrow lines, low roughness in the trenches. -
Top view: low roughness in the trenches. -
30 dg view: low roughness in the trenches -
30 dg view: low roughness in the trenches -
Top view: low roughness in trench and in the large area
