Specific Process Knowledge/Etch/III-V ICP/InP-InGaAsP-InGaAs: Difference between revisions
| Line 74: | Line 74: | ||
===Etching of an InP piece on SiO2 carrier=== | ===Etching of an InP piece on SiO2 carrier=== | ||
InP piece patterned with SiO2. The piece was etched on top of a Si wafer coated with SiO2 without bonding. The recipe "InP etch" was used. The roughness looks low in the bottom of the etched areas, even in the large open areas. | InP piece patterned with SiO2. The piece was etched on top of a Si wafer coated with SiO2 without bonding. The recipe "InP etch" was used. The roughness looks low in the bottom of the etched areas, even in the large open areas. | ||
<gallery> | |||
Image:S4_00.jpg | |||
Image:S4_01.jpg | |||
Image:S4_02.jpg | |||
Image:S4_03.jpg | |||
Image:S4_30dg_midt_10.jpg | |||
Image:S4_30dg_midt_11.jpg | |||
Image:S4_30dg08.jpg | |||
Image:S4_30dg09.jpg | |||
Image:S4_midt_04.jpg | |||
Image:S4_midt_05.jpg | |||
Image:S4_midt_06.jpg | |||
Image:S4_midt_07.jpg | |||
</gallery> | |||