Specific Process Knowledge/Etch/III-V ICP/InP-InGaAsP-InGaAs: Difference between revisions

From LabAdviser
Bghe (talk | contribs)
Bghe (talk | contribs)
Line 59: Line 59:


==InP etching June 2018==
==InP etching June 2018==
===With InP piece on Si carrier===
===Etching of an InP piece on Si carrier===
InP piece patterned with SiO2. The pice was etched on top of a Si wafer without bonding. The "InP etch" was used.
InP piece patterned with SiO2. The piece was etched on top of a Si wafer without bonding. The recipe "InP etch" was used. The roughness looks high in the bottom of the etched areas, especially the large open areas.
<gallery caption="Result of InP etching."  widths="500px" heights="400px" perrow="3">
<gallery caption="Result of InP etching."  widths="500px" heights="400px" perrow="3">



Revision as of 12:23, 19 June 2018

Feedback to this page: click here

InP/InGaAsP/InGaAs etch

Unselective etch for large sized features and small aspect ratios by David Larsson, DTU Photonics, 2011

Recipe InP Etch 1/InP Precond 1
Cl2 flow 20 sccm
N2 flow 40 sccm
Ar flow 10 sccm
Platen power 100 W
Coil power 500 W
Pressure 2 mTorr
Platen chiller temperature 180 oC


Results (InP Etch 1)
Etch rate 500-600 nm/min
Sidewall angle 86-87 o
Selectivity (InP:SiO2, InP:HSQ) 50:1

InP etching June 2018

Etching of an InP piece on Si carrier

InP piece patterned with SiO2. The piece was etched on top of a Si wafer without bonding. The recipe "InP etch" was used. The roughness looks high in the bottom of the etched areas, especially the large open areas.