Specific Process Knowledge/Etch/III-V ICP/InP-InGaAsP-InGaAs: Difference between revisions
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==InP etching June 2018== | ==InP etching June 2018== | ||
===With InP piece on Si carrier=== | ===With InP piece on Si carrier=== | ||
InP piece patterned with SiO2. The pice was etched on | InP piece patterned with SiO2. The pice was etched on top of a Si wafer without bonding. The "InP etch" was used. | ||
<gallery caption="Result of InP etching." widths="500px" heights="400px" perrow="3"> | <gallery caption="Result of InP etching." widths="500px" heights="400px" perrow="3"> | ||
Image:S1_30dg_09.jpg | Image:S1_30dg_09.jpg|low roughness in narrow trenched | ||
Image:S1_30dg_10.jpg | Image:S1_30dg_10.jpg|low roughness in narrow trenched | ||
Image:S1_30dg_midt_14.jpg | Image:S1_30dg_midt_14.jpg|A little higher roughnedd is larger trences | ||
Image:S1_30dg_midt_13.jpg | Image:S1_30dg_midt_13.jpg|Much larger roughness in open areas | ||
Image:S1_30dg_midt_12.jpg | Image:S1_30dg_midt_12.jpg|Zoom in on the large roughness | ||
Image:S1_30dg_midt_11.jpg | Image:S1_30dg_midt_11.jpg|closed look at the large roughness in the open areas. | ||
</gallery> | </gallery> | ||