Specific Process Knowledge/Etch/KOH Etch: Difference between revisions

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*[[/ProcessInfo#Mixing KOH|How to mix KOH]]
*[[/ProcessInfo#Mixing KOH|How to mix KOH]]
*[[/ProcessInfo#Theory|Crystal orientation dependency]]
*[[/ProcessInfo#Theory|Crystal orientation dependency]]
===Quality Control (QC) for the KOH Si etching baths.===
{| border="1" cellspacing="2" cellpadding="2" colspan="3"
|bgcolor="#98FB98" |'''Quality Control (QC) for Si Etch 01, and Si Etch 02'''
|-
|
*[http://labmanager.danchip.dtu.dk/d4Show.php?id=3203&mach=9 The QC procedure for Si Etch: 01]<br>
*[http://labmanager.danchip.dtu.dk/d4Show.php?id=1565&mach=248 The QC procedure for Si Etch: 01]<br>
*[http://labmanager.danchip.dtu.dk/view_binary.php?type=data&mach=49 The newest QC data for KOH2]<br>
*[http://labmanager.danchip.dtu.dk/view_binary.php?type=data&mach=248 The newest QC data for KOH3]<br>
{| {{table}}
| align="center" |
{| border="1" cellspacing="1" cellpadding="2"  align="center" style="width:200px"
! QC Recipe:
! &nbsp;
|-
| Solution
|28 wt% KOH
|-
|Temperature
|80°C
|-
|Time
|90 min
|-
|Substrate
|Si (100)
|-|-
|Masking
|No masking
|-
|}
| align="center" valign="top"|
{| border="3" cellspacing="1" cellpadding="2" align="center" style="width:500px"
!QC limits
!Si Etch 01
!Si Etch 02
|-
|Etch rate in Si(100)
|1.3 ± 0.1 µm/min
|1.29 ± 0.06 µm/min
|-
|Roughness
| not measured
| not measured
|-
|Nonuniformity
|< 3%
|< 3%
|-
|}
|-
|}
|}
<br clear="all" />


==KOH etching baths==
==KOH etching baths==

Revision as of 15:56, 13 March 2018

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Si etch - Anisotropic silicon etch

KOH belongs to the family of anisotropic Si-etchants based on aqueous alkaline solutions. The anisotropy stems from the different etch rates in different crystal directions. The {111}-planes are almost inert whereas the etch rates of e.g. {100}- and {110}-planes are several orders of magnitude faster.

KOH-etching is a highly versatile and cheap way to realize micro mechanical structures if you can live with the necessary Si3N4- or SiO2-masking materials and the potassium contamination of the surface. The latter necessitates in most cases a wet post-clean ('7-up' or RCA-clean) if the wafer is to be processed further.

At Danchip we use as a standard a 28 wt% KOH. The etch rate - and the selectivity towards a SiO2-mask - is depending on the temperature. We normally use T=80 oC but may choose to reduce this to e.g. 60 oC or 70 oC in case of a high-precision timed etch (e.g. defining a thin membrane). In some cases we recommend to saturate the standard 28 wt% KOH with IPA with an etch temperature at T=70 oC (reduce evaporation of IPA). One example is for boron etch-stop, where the selectivity towards the boron-doped silicon is improved compared to the standard etch. Etching with IPA added to the KOH solution can be done in KOH fumehood.


The user manuals, quality control procedures and results, user APVs, technical information and contact information can be found in LabManager:


Si Etch 1: KOH info page in LabManager,

Si Etch 2: KOH info page in LabManager,

Si Etch 3: KOH info page in LabManager

Process Information

KOH etching baths

Key facts for the different etch baths available at Danchip are resumed in the table:


Equipment Si Etch 01 Si Etch 02 Si Etch 03 Fume hood 06
Purpose
  • Etch of Silicon in 28 wt% KOH
  • Etch of Silicon in 28 wt% KOH
  • Etch of Silicon in 28 wt% KOH
  • Etch of Silicon in 28 wt% KOH

The bath is dedicated wafer with electroplated Nickel or otherwise dirty wafers

Link to safety APV and KBA
Performance Etch rates in crystalline silicon (100)
  • 0.4 µm/min (60 °C)
  • 0.7 µm/min (70 °C)
  • 1.3 µm/min (80 °C)
  • 0.4 µm/min (60 °C)
  • 0.7 µm/min (70 °C)
  • 1.3 µm/min (80 °C)
  • 0.4 µm/min (60 °C)
  • 0.7 µm/min (70 °C)
  • 1.3 µm/min (80 °C)
Etch rates in crystalline silicon (110)
  • 2.5 µm/min (80 °C)
  • 2.5 µm/min (80 °C)
  • 2.5 µm/min (80 °C)
Etch rates in Thermal SiO2
  • Theoretical values:
  • 1.2 nm/min (60 °C)
  • 6 nm/min (80 °C)
  • Theoretical values:
  • 1.2 nm/min (60 °C)
  • 6 nm/min (80 °C)
  • Theoretical values:
  • 1.2 nm/min (60 °C)
  • 6 nm/min (80 °C)
Etch rates in other oxides

.

yannickseis@nbi.ku nov. 2017 @80 °C:

  • BPSG from PECVD4: 311nm in about 3 min
  • Waveguide oxide from PECVD4: 320nm etched in 26 min
  • TEOS oxide from furnace: 300nm etched in 11 min

.

Etch rates in SiN
Roughness
  • Typical: 100-600 Å
  • Typical: 100-600 Å
  • May be high due to contamination and poor controlled concentration of the KOH solution
Anisotropy
  • The etch rate is very dependent on the crystal orientation of the silicon.
  • The etch rate is very dependent on the crystal orientation of the silicon.
  • The etch rate is very dependent on the crystal orientation of the silicon.
Process parameter range Chemical solution
  • Mixing ratios giving 28 wt% KOH solutions

KOH:H2O - 500 g : 1000 ml, when using pills KOH:H2O - 1000 ml: 1200 ml, when using premixed 50% KOH solution

  • Mixing ratios giving 28 wt% KOH solutions

KOH:H2O - 500 g : 1000 ml, when using pills KOH:H2O - 1000 ml: 1200 ml, when using premixed 50% KOH solution

  • Custom made
Temperature
  • Max 80 °C (standard etch)
  • Max 80 °C
  • Max 80 °C
Substrates Batch size
  • 1-25 wafers at a time
  • 1-25 wafers at a time
  • 1-7 wafers at a time
Size of substrate
  • 4”-6" wafers
  • 4”-6" wafers
  • 2” wafers
  • 4” wafers
  • 6” wafers
  • Small pieces
Allowed materials
  • Silicon
  • Silicon oxide
  • Silicon (oxy)nitride
  • Silicon
  • Silicon oxide
  • Silicon (oxy)nitride
  • All except for Polymers
Masking material
  • Stoichiometric Si3N4
  • Silicon rich nitride SiN
  • PECVD Si3N4
  • Thermal SiO2
  • Stoichiometric Si3N4
  • Silicon rich nitride SiN
  • PECVD Si3N4
  • Thermal SiO2
  • Stoichiometric Si3N4
  • Silicon rich nitride SiN
  • PECVD Si3N4
  • Thermal SiO2

1 Measured by Eric Jensen from DTU-Nanotech, October 2013.

Definition of structures

Due to the almost inert (111)-planes it is possible by KOH etching to realize high aspect ratio structures in sigle crytalline silicon using the (111)-planes as sidewalls. In Si(100) these sidewalls are inclined - 54.7o with respect to the (100) surface - whereas in Si(110) the sidewalls are vertical (see figures below).


For Si(100), the relation between the width of the bottom of the etched groove (Wb) and the width of the opening (Wo) at the wafer surface in a groove etched to the depth l is given by:


Failed to parse (SVG (MathML can be enabled via browser plugin): Invalid response ("Math extension cannot connect to Restbase.") from server "https://wikimedia.org/api/rest_v1/":): {\displaystyle W_b = W_o - 2lcot(54.7^o) = W_o - \sqrt{2} l}



Definition of <110> alignment structures

The etch rate dependence on the crystallographic planes can be used to determine the <110> crystal directions with high precision (better than +/- 0.05 o). A fast method for doing this, using the symmetric under-etching behavior around but not at the <110>-directions, was described by Vangbo and Bäcklund in J. Micromech. Microeng.6 (1996), 279-284. High-precision control of the <110>-direction during alignment can be necessary in order to control the dimensions of KOH-etched structures (e.g. precise control of V-groove dimensions). A dedicated mask (MASK NAME) has been designed for this purpose.


Etch rates: Empirical formula (Seidl et al)

The following empirical formula can be used for concentrations in the range of 10-60 wt%:

R = k0 [H2O]4 [KOH]0.25 e-Ea/kT,

where k0 = 2480 µm/hr (mol/l)-4.25, Ea = 0.595 eV for Si(100)

and k0 = 4500 µm/hr (mol/l)-4.25, Ea = 0.60 eV for Si(110)