Specific Process Knowledge/Etch/ASE (Advanced Silicon Etch): Difference between revisions

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= The ASE =
= The ASE =


[[image:ASE.jpg|300x300px|right|thumb|The ICP-DRIE tool at Danchip: STS ASE - positioned in cleanroom B-1]]
[[image:ASE.jpg|300x300px|right|thumb|STS ASE - positioned in cleanroom B-1]]


The ASE was the first ICP (Inductively coupled plasma) tool at Danchip. It was manufactured by STS and is called the ASE (Advanced Silicon Etcher). Originally the main purpose of the ASE was etching of silicon using the Bosch process. However, after the acquisition of the [[Specific Process Knowledge/Etch/DRIE-Pegasus|DRIE-Pegasus]] and the retirement of our old RIE's the ASE will only serve as a "dirty" plasma etcher, etching silicon, Silicon oxide and silicon nitride on wafers with small amount of metals exposed and as a polymer etcher. The rule is that samples with up to 4 cm2 of metal on the surface will be allowed to process. Extra gasses was been added to the machine during the summer in 2017 to allow SiO2 and SiN etching. Using these gasses may affect the conditioning of the chamber and thereby the stability of processes. Any clean processes and sensitive processes should take place in to the DRIEs or elsewhere.
The ASE was the first ICP (Inductively coupled plasma) tool at Danchip. It was manufactured by STS and is called the ASE (Advanced Silicon Etcher). Originally the main purpose of the ASE was etching of silicon using the Bosch process. However, after the acquisition of the [[Specific Process Knowledge/Etch/DRIE-Pegasus|DRIE-Pegasus]] and the retirement of our old RIE's the ASE will only serve as a "dirty" plasma etcher, etching silicon, Silicon oxide and silicon nitride on wafers with small amount of metals exposed and as a polymer etcher. The rule is that samples with up to 4 cm2 of metal on the surface will be allowed to process. Extra gasses was been added to the machine during the summer in 2017 to allow SiO2 and SiN etching. Using these gasses may affect the conditioning of the chamber and thereby the stability of processes. Any clean processes and sensitive processes should take place in to the DRIEs or elsewhere.

Revision as of 08:47, 24 January 2018

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The ASE

STS ASE - positioned in cleanroom B-1

The ASE was the first ICP (Inductively coupled plasma) tool at Danchip. It was manufactured by STS and is called the ASE (Advanced Silicon Etcher). Originally the main purpose of the ASE was etching of silicon using the Bosch process. However, after the acquisition of the DRIE-Pegasus and the retirement of our old RIE's the ASE will only serve as a "dirty" plasma etcher, etching silicon, Silicon oxide and silicon nitride on wafers with small amount of metals exposed and as a polymer etcher. The rule is that samples with up to 4 cm2 of metal on the surface will be allowed to process. Extra gasses was been added to the machine during the summer in 2017 to allow SiO2 and SiN etching. Using these gasses may affect the conditioning of the chamber and thereby the stability of processes. Any clean processes and sensitive processes should take place in to the DRIEs or elsewhere.


In the case of the silicon etching on the ASE, an etch phase with SF6 and O2 alternates with a passivation phase with C4F8.

The user manual, quality control procedure and results, user APV(s), technical information and contact information can be found in LabManager:

Equipment info in LabManager

Process information

An overview of the performance of the ASE and some process related parameters

Purpose Dry etch of
  • Silicon
  • Thin layers of Silicon oxide and silicon nitride
  • Polymers such as polyimide, PDMS, PMMA, BCB and resists
Performance Etch rates
  • Silicon: ~0-15 µm/min (depending on features size and etch load)
  • Silicon oxide: <0.1 µm/min
  • Silicon nitride: <0.1 µm/min
Anisotropy
  • Good
Process parameter range Process pressure
  • ~0.1-95 mTorr
Gas flows
  • SF6: 0-600 sccm
  • O2: 0-99 sccm
  • C4F8: 0-300 sccm
  • Ar: 0-142 sccm
  • CF4: 0-99.9 sccm
  • CHF3: 0-99.9 sccm
  • H2: 0-40 sccm
  • He: 0-500 sccm
Substrates Batch size
  • 1 6" wafer per run (requires hardware change)
  • 1 4" wafer per run
  • 1 2" wafer per run (requires carrier)
  • Or several smaller pieces on a carrier wafer
Substrate material allowed
  • Silicon wafers
    • with layers of silicon oxide or silicon (oxy)nitride
  • Quartz wafers
Possible masking material
  • Photoresist/e-beam resist
  • PolySilicon
  • Silicon oxide or silicon (oxy)nitride
  • Aluminium