Specific Process Knowledge/Etch/Etching of Bulk Glass

At Danchip, we have two types of bulk glass substrates: Borosilicate glass (Borofloat 33 (like pyrex)) and fused silicate glass which in cleanliness is similar to quartz. Both types are etched wet in a special set-up placed in a fumehood using a strong HF-solution (isotropic etch). The set-up consists of a 5 l plasic beaker placed on a stirring plate (magnetic stirring) and a special horizontal wafer holder. Normally a 40% pre-mixed HF solution is used.

Masking materials and pre-treatment of the glass surface prior to the deposition of the masking material is a special concern in particular for deep etchings (> 10µm).

Due to the high cleanliness fused silica is allowed access to basically all machines meaning that e.g. LPCVD silicon can be deposited as masking material. This is an excellent mask even for quite deep etchings.

Regarding borosilicate glass masking is more tricky. The follwing sequence has been used with some success (using sputtered silicon from the Alcatel):

• Piranha clean
• Bake-out at 250 C (>2,5 hours)
• Plasma ashing
• Sputter-deposit in Alcatel: Power: 550W, Ar-pressure: 10$^{-2}$ mbar (base pressure: 10$^{-6}$ mbar)
• Patterning of the silicon using either wet (poly-etch) or dry etching

40% HF 3µm/min Beaker Maske?

Wet HF-etch of bulk glass

	Fused silica	Borofloat glass
General description	40% pre-mixed HF	40% pre-mixed HF
Possible masking materials	LPCVD silicon	Sputtered silicon (Alcatel)
Etch rate	~700 nm/min (patterned silica, slow stirring) ~800 nm/min (non-patterned silica, slow stirring)	~3,9 µm/min
Uniformity	~ 2% (slow stirring, horizontal wafer)
Batch size	1-25 wafers at a time	1 wafer at a time
Size of substrate	4" wafers	4" wafers or smaller pieces
Allowed materials	Silicon Silicon Oxide Silicon Nitride Silicon Oxynitride Photoresist Blue film Gold (Au) and Nickel (Ni) (but only in BHF2 (KOH)!)	Silicon Silicon Oxide Silicon Nitride Silicon Oxynitride Photoresist E-beam resist Aluminium Chromium (ONLY RIE2!) Other metals that covers less the 5% of the wafer area (ONLY RIE2!)