Specific Process Knowledge/Etch/ICP Metal Etcher/silicon oxide: Difference between revisions

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==SiO2 etch nLOF==
==SiO2 etch nLOF==
{| border="2" cellspacing="2" cellpadding="3"
|-style="background:Gray; color:White"
!Parameter
!Resist mask
|-
|Coil Power [W]
|800
|-
|Platen Power [W]
|100
|-
|Platen temperature [<sup>o</sup>C]
|0
|-
|CF<sub>4</sub> flow [sccm]
|30
|-
|H<sub>2</sub> flow [sccm]
|10
|-
|Pressure [mTorr]
|4
|-
|}
{| border="2" cellspacing="2" cellpadding="3"
|-style="background:Black; color:White"
!Results
!Test on wafer with 50% load (Travka 50), by BGHE @danchip
|-
|Etch rate of thermal oxide
|'''>110 nm/min (50% etch load) (09-03-2015)'''
|
|-
|Selectivity to  resist [:1]
|'''<0.7:1''' (SiO2:resist)
|-
|Wafer uniformity (100mm)
|
|-
|Profile [<sup>o</sup>]
|Not known
|-
|Wafer uniformity map (click on the image to view a larger image)
|Not Known
|-
|SEM profile images
|NONE
|-
|Etch rate in nLOF resist
|1.6µm was removed after 10min
|-
|}

Revision as of 14:42, 9 March 2015

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It is possible to etch SiO2 in the ICP metal etcher but it is not designed for it and the results are not fantastic. It is a challenge to get a good selectivity to resist (typically in the range of 1:1 or worse) and it is probably not possible to get a profile angle of 90 degrees. More likely about 75-85 degrees.

Slow etch of SiO2 with resist as masking material - using a 6" carrier wafer with recess

This recipe can be used for slow etching of SiO2 with resist as masking material. Here are some test results presented.

Parameter Resist mask
Coil Power [W] 200
Platen Power [W] 25
Platen temperature [oC] 0
CF4 flow [sccm] 20
H2 flow [sccm] 10
Pressure [mTorr] 3


Results Test on wafer with 50% load (Travka 50), by BGHE @danchip 100% load on 100mm wafers with Barc and KRF (no mask)
Etch rate of thermal oxide 44.1 nm/min (50% etch load) (01-02-2014)
Selectivity to resist [:1] ~0.9 (SiO2:resist) ~1.25:1 (Barc:KRF)
Wafer uniformity (100mm) ±1.6% (01-02-2014)
Profile [o] Take a look at the images but be aware that the resist profile was not good to begin with.
Wafer uniformity map (click on the image to view a larger image)
Contour plot of the etch rate over the wafer, 9 points measured
SEM profile images
  • Resist profile before etch
    Resist profile before etch
  • Resist profiler after etch 01-02-2014.
    Resist profiler after etch 01-02-2014.
  • Resist profiler after etch 01-02-2014. No line width reduction observed.
    Resist profiler after etch 01-02-2014. No line width reduction observed.
Etch rate in barc 50 nm/min (2014-09-09)
Etch rate in KRF resist 40 nm/min (2014-09-09)


SiO2 etch using DUV mask


SiO2 etch nLOF

Parameter Resist mask
Coil Power [W] 800
Platen Power [W] 100
Platen temperature [oC] 0
CF4 flow [sccm] 30
H2 flow [sccm] 10
Pressure [mTorr] 4


Results Test on wafer with 50% load (Travka 50), by BGHE @danchip
Etch rate of thermal oxide >110 nm/min (50% etch load) (09-03-2015)
Selectivity to resist [:1] <0.7:1 (SiO2:resist)
Wafer uniformity (100mm)
Profile [o] Not known
Wafer uniformity map (click on the image to view a larger image) Not Known
SEM profile images NONE
Etch rate in nLOF resist 1.6µm was removed after 10min
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