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Specific Process Knowledge/Lithography/CSAR: Difference between revisions

Tigre (talk | contribs)
Tigre (talk | contribs)
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|4" Si wafer with non-patterned CSAR, postbaked 60 sec @ 130 degC
|4" Si wafer with non-patterned CSAR, <br>postbaked 60 sec @ 130 degC
|nano1.42
|nano1.42
|56.5 (based on 2 runs)
|56.5 (based on 2 runs)
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|1/4 4" Si wafer with non-patterned CSAR, not crystal bonded to carrier
|1/4 4" Si wafer with non-patterned CSAR, <br>not crystal bonded to carrier
|nano1.42
|nano1.42
|83.3 (based on 3 runs)
|83.3 (based on 3 runs)
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|1/4 4" Si wafer with non-patterned CSAR, crystal bonded to 4" Si carrier
|1/4 4" Si wafer with non-patterned CSAR, <br>crystal bonded to 4" Si carrier
|nano1.42
|nano1.42
|54 (based on 1 run)
|54 (based on 1 run)
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|Slice of Si wafer with nano-patterned CSAR, crystal bonded to 4" Si carrier
|Slice of Si wafer with nano-patterned CSAR, <br>crystal bonded to 4" Si carrier
|nano1.42
|nano1.42
|54 (based on 1 run)
|54 (based on 1 run)
|100 nm structures: 200 (based on 1 run)
|100 nm structures: 200 (based on 1 run)
50 nm structures:
<br>50 nm structures:
30 nm structues:  
<br>30 nm structues:  
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