Specific Process Knowledge/Bonding: Difference between revisions

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 *[[/Anodic bonding|Anodic bonding]]
-===Comparing the three bonding methods in the EVG NIL===
+==Comparison table for 3 bonding methods in EVG NIL==
-{| border="2" cellspacing="0" cellpadding="4" align="center"
-!.
-![[/Eutectic bonding|Eutectic bonding]]
-![[/Fusion bonding|Fusion bonding]]
-![[/Anodic bonding|Anodic bonding]]
-|- valign="top"
-|'''General description'''
-|For bonding two substrates by use of an interphase that makes an eutecticum.
-|For bonding two identical materials.
-|For bonding Si and Glass.
-|-valign="top"
-|'''Bonding temperature'''
-|Depending on the eutecticum 310°C  to 400°C .
-|Depending on defects 50°C  to 400°C .
-|Depending on the voltage 300°C to 500°C  Standard is 400°C .
-|-valign="top"
-|'''Annnealing temperature'''
-|No annealing
-|1000°C  in the bond furnace C3
-|No annealing
-|-valign="top"
-|'''Materials possible to bond'''
-|Bonding of substrates is done by use of the eutectica Au/Si, Au/Sn and Au/Sn/Ni
-|Si/Si, SiO<math>_2</math>/SiO<math>_2</math>
-|Si/Pyrex (glass)
-|-valign="top"
-|'''Substrate size'''
-|Up to 6" (aligning only possible for 4" and 6")
-|Up to 6" (aligning only possible for 4" and 6")
-|Up to 6" (aligning only possible for 4" and 6")
-|-valign="top"
-|'''Cleaning'''
-|Cleaning by N2.
-|Wet chemical cleaning, [[Specific Process Knowledge/Wafer cleaning/IMEC|IMEC]].
-|Cleaning by N2.
-|-valign="top"
-|'''IR alignment'''
-|Double side polished wafers.
-|Double side polished wafers.
-|Not relevant.
-|-
+{| border="2" cellspacing="0" cellpadding="2"
-|}
+!colspan="1" border="none" style="background:silver; color:black;" align="center"|
+|style="background:WhiteSmoke; color:black"|<b>[[/Eutectic bonding|Eutectic bonding]]</b>
+|style="background:WhiteSmoke; color:black"|<b>[[/Fusion bonding|Fusion bonding]]</b>
+|style="background:WhiteSmoke; color:black"|<b>[[/Anodic bonding|Anodic bonding]]</b>
+|-
+!style="background:silver; width:100px; color:black;" align="center"|General description
+|style="background:WhiteSmoke; color:black"|
+For bonding two substrates by use of an interphase that makes an eutecticum.
+|style="background:WhiteSmoke; color:black"|
+For bonding two identical materials.
+|style="background:WhiteSmoke; color:black"|
+For bonding Si and Glass.
+|-
+!style="background:silver; color:black" align="center" valign="center"|Bonding temperature
+|style="background:WhiteSmoke; color:black"|
+Depending on the eutecticum 310°C to 400°C.
+|style="background:WhiteSmoke; color:black"|
+Depending on defects 50°C to 400°C.
+|style="background:WhiteSmoke; color:black"|
+Depending on the voltage 300°C to 500°C Standard is 400°C.
+|-
+!style="background:silver; color:black" align="center" valign="center"|Annealing temperature
+|style="background:WhiteSmoke; color:black"|
+No annealing
+|style="background:WhiteSmoke; color:black"|
+°C in the bond furnace C3.
+|style="background:WhiteSmoke; color:black"|
+No annealing
+|-
+!style="background:silver; color:black" align="center" valign="center"|Materials possible to bond
+|style="background:WhiteSmoke; color:black"|
+Bonding of substrates is done by use of the eutectica Au/Si, Au/Sn and Au/Sn/Ni
+|style="background:WhiteSmoke; color:black"|
+Si/Si, SiO2/SiO2
+|style="background:WhiteSmoke; color:black"|
+Si/Pyrex (glass)
+|-
+!style="background:silver; color:black" align="center" valign="center"|Substrate size
+|style="background:WhiteSmoke; color:black"|
+Up to 6" (aligning only possible for 4" and 6")
+|style="background:WhiteSmoke; color:black"|
+Up to 6" (aligning only possible for 4" and 6")
+|style="background:WhiteSmoke; color:black"|
+Up to 6" (aligning only possible for 4" and 6")
+|-
+!style="background:silver; color:black" align="center" valign="center"|Cleaning
+|style="background:WhiteSmoke; color:black"|
+Cleaning by N2.
+|style="background:WhiteSmoke; color:black"|
+Wet chemical cleaning, [[Specific Process Knowledge/Wafer cleaning/IMEC|IMEC]].
+|style="background:WhiteSmoke; color:black"|
+Cleaning by N2.
+|-
+!style="background:silver; color:black" align="center" valign="center"|IR alignment
+|style="background:WhiteSmoke; color:black"|
+Double side polished wafers.
+|style="background:WhiteSmoke; color:black"|
+Double side polished wafers.
+|style="background:WhiteSmoke; color:black"|
+Not relevant.
+|-
+<br clear="all" />
 == Choose equipment ==
 *[[/EVG NIL|EVG NIL]]
 *[[Specific Process Knowledge/Thermal Process/C3 Anneal-bond furnace|C3 furnace anneal bond]]