Specific Process Knowledge/Etch/Etching of Silicon/Si etch using ASE: Difference between revisions
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===Etch of nano sized structures=== | ===Etch of nano sized structures=== | ||
*See pxnano2 and comparison with nanotech on the Pegasus: [[Specific Process Knowledge/Etch/DRIE-Pegasus/nanoetch/nano142-pxnano2]] | |||
Older work: | |||
Three different examples of etch are shown here. The masking material was zep520A (80 nm). | Three different examples of etch are shown here. The masking material was zep520A (80 nm). | ||
Revision as of 13:34, 25 August 2015
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The Bosch process: Etching of silicon
The Bosch process uses alternation between an etch cycle and a passivation cycle. Introducing a passivation step in an etch process is very beneficial for the control of the angle of the sidewalls in the etch process because it allows us to cover them with a protective layer that suppresses the isotropic etching. Combined with the high plasma density in the ICP chamber, the excellent sidewall control enables us to etch high aspect ratio structures in silicon with very high etch rates.
In the case of the silicon etching on the ASE, an etch phase with SF6 and O2 alternates with a passivation phase with C4F8.
Quality control procedure on the ASE
Two recipes have been optimized for the ASE. Their specification is on a 10 % etch load wafer with trenches.
- Shallolr: The shallow etch process will etch a 2 µm opening down to make a 20 µm trench.
- Deepetch: The deep etch process will etch a 50 µm opening down to make a 300 µm trench.
The standardization procedure on the ASE covers these two etches.
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Recipes on the ASE
Shallolr
The shallolr recipe is designed to etch features (with sizes above 1 µm) in silicon down to a depth that ranges from a few microns to some 50 microns. (If you need to etch deeper use Deepetch or more shallow, see Nanoetches.) It is specified to etch a 2 µm wide trench down to a depth of 20 µm on a wafer that has a global/local etch opening density of 10%.
The recipe is given above.
The process runs for 31 cycles (5:56 mins). The fact that it's Bosch process is clear from the scallops on the sidewalls - one should be able to count 31 of them.
- Standardization images of the shallolr recipe
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The profile of a 2 µm trench -
The profile of a 50 µm trench
The process is designed to reach 20 µm down in a 2 µm trench but as is clear from the image of the corresponding 50 µm trench, this one is etched deeper. The reason is the so called Aspect Ratio Dependent Etching or ARDE: See below.
Deepetch
The deepetch recipe is designed to etch features (with sizes 2 µm) in silicon down to a depth that ranges from some 50 microns to hundreds of microns. (If you need to etch less, use shallow or Nanoetches.) It is specified to etch a 50 µm wide trench down to a depth of 300 µm on a wafer that has a global/local etch density of 10%.
- Standardization images of the deepetch recipe
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The profile of a 2 µm trench -
The profile of a 50 µm trench
As is clear from the two images ARDE also plays a role in this case: The 2 µm trench (widened to about 5-6 µm because of undercut/underetching) is only etched 150 µm.
Process development
Etch of nano sized structures
- See pxnano2 and comparison with nanotech on the Pegasus: Specific Process Knowledge/Etch/DRIE-Pegasus/nanoetch/nano142-pxnano2
Older work: Three different examples of etch are shown here. The masking material was zep520A (80 nm).
| Vertical sidewalls | Low ARDE | Positive tappered side walls |
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Etch cycle
Dep. Cycle
Results:
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Etch cycle
Dep. Cycle
Results:
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Etch cycle
Dep. Cycle
Results:
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