Specific Process Knowledge/Etch/Etching of Silicon/Si etch using ASE: Difference between revisions

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 In the case of the silicon etching on the ASE, an etch phase with SF<sub>6</sub> and O<sub>2</sub> alternates with a passivation phase with C<sub>4</sub>F<sub>8</sub>.
-=== The two standard silicon etch recipes ===
-Two recipes have been optimized for the ASE. Their specification is on a 10 % etch load wafer with trenches.
-* '''Shallolr''': The shallow etch process will etch a 2 µm opening down to make a 20 µm trench.
-* '''Deepetch''': The deep etch process will etch a 50 µm opening down to make a 300 µm trench.
-The standardization procedure on the ASE covers these two etches.
 == Quality control procedure on the ASE==