Specific Process Knowledge/Etch/ASE (Advanced Silicon Etch): Difference between revisions

From LabAdviser
Jml (talk | contribs)
Jml (talk | contribs)
Line 19: Line 19:
|style="background:LightGrey; color:black"|Dry etch of ||style="background:WhiteSmoke; color:black"|
|style="background:LightGrey; color:black"|Dry etch of ||style="background:WhiteSmoke; color:black"|
*Silicon
*Silicon
*Silicon oxide
*Silicon (oxy)nitride
|-
|-
!style="background:silver; color:black" align="left"|Performance
!style="background:silver; color:black" align="left"|Performance
|style="background:LightGrey; color:black"|Etch rates||style="background:WhiteSmoke; color:black"|
|style="background:LightGrey; color:black"|Etch rates||style="background:WhiteSmoke; color:black"|
*Silicon: ~0.04-0.8 µm/min
*Silicon: ~4-6 µm/min (depending on features size and etch load)
*Silicon oxide:~0.02-0.15 µm/min
*Silicon (oxy)nitride:~0.02-? µm/min
|-
|-
|style="background:silver; color:black" |.||style="background:LightGrey; color:black"|Anisotropy||style="background:WhiteSmoke; color:black"|
|style="background:silver; color:black" |.||style="background:LightGrey; color:black"|Anisotropy||style="background:WhiteSmoke; color:black"|
Line 33: Line 29:
!style="background:silver; color:black" align="left"|Process parameter range
!style="background:silver; color:black" align="left"|Process parameter range
|style="background:LightGrey; color:black"|Process pressure||style="background:WhiteSmoke; color:black"|
|style="background:LightGrey; color:black"|Process pressure||style="background:WhiteSmoke; color:black"|
*~20-200 mTorr
*~0.1-95 mTorr
|-
|-
|style="background:silver; color:black"|.||style="background:LightGrey; color:black"|Gas flows
|style="background:silver; color:black"|.||style="background:LightGrey; color:black"|Gas flows
|style="background:WhiteSmoke; color:black"|
|style="background:WhiteSmoke; color:black"|
*SF<math>_6</math>: 0-130 sccm
*SF<math>_6</math>: 0-600 sccm
*O<math>_2</math>: 0-100 sccm
*O<math>_2</math>: 0-100 sccm
*CHF<math>_3</math>: 0-100 sccm
*C<math>_4</math>F<math>_8</math>: 0-300 sccm
*CF<math>_4</math>: 0-84 sccm
*Ar: 0-100 sccm
*H<math>_2</math>: ?sccm
*Ar: 0-145 sccm
*N<math>_2</math>: 0-100 sccm
*C<math>_2</math>F<math>_6</math>: 0-24 sccm
|-
|-
!style="background:silver; color:black" align="left"|Substrates
!style="background:silver; color:black" align="left"|Substrates
|style="background:LightGrey; color:black"|Batch size
|style="background:LightGrey; color:black"|Batch size
|style="background:WhiteSmoke; color:black"|
|style="background:WhiteSmoke; color:black"|
*1 6" wafer per run
*1 4" wafer per run
*1 4" wafer per run
*1 2" wafer per run
*1 2" wafer per run
*Or several smaller pieces
*Or several smaller pieces on a carrier wafer
|-
|-
|style="background:silver; color:black"|.|| style="background:LightGrey; color:black"|Substrate material allowed
|style="background:silver; color:black"|.|| style="background:LightGrey; color:black"|Substrate material allowed
Line 62: Line 55:
|style="background:WhiteSmoke; color:black"|
|style="background:WhiteSmoke; color:black"|
*Photoresist/e-beam resist
*Photoresist/e-beam resist
*Silicon/PolySi
*PolySilicon
*Silicon oxide or silicon (oxy)nitride
*Silicon oxide or silicon (oxy)nitride
*Aluminium
*Aluminium
*Other metals if the coverage is <5% of the wafer area (ONLY PECVD3!)
|-  
|-  
|}
|}

Revision as of 16:01, 19 December 2007

The ASE

The ICP-DRIE tool at Danchip: STS ASE - positioned in cleanroom2

The ICP-DRIE (Inductively Coupled Plasma - Deep Reactive Ion Etcher) tool at Danchip is manufactured by STS and is called the ASE (Advanced Silicon Etcher). The main purpose of the ASE is etching of silicon using Bosch process.

The Bosch process: Etching of silicon

The Bosch process uses alternation between an etch cycle and a passivation cycle. Introducing a passivation step in an etch process is very beneficial for the control of the angle of the sidewalls in the etch process because it allows us to cover them with a protective layer that suppresses the isotropic etching. Combined with the high plasma density in the ICP chamber, the excellent sidewall control enables us to etch high aspect ratio structures in silicon with very high etch rates.

In the case of the silicon etching on the ASE, an etch phase with SF6 and O2 alternates with a passivation phase with C4F8.


A rough overview of the performance of the RIE´s and some process related parameters

Purpose Dry etch of
  • Silicon
Performance Etch rates
  • Silicon: ~4-6 µm/min (depending on features size and etch load)
. Anisotropy
  • Can vary from isotropic to anisotropic with vertical sidewalls and on to a physical etch were the sidewalls are angled but without etching under the mask.
Process parameter range Process pressure
  • ~0.1-95 mTorr
. Gas flows
  • SF: 0-600 sccm
  • O: 0-100 sccm
  • CF: 0-300 sccm
  • Ar: 0-100 sccm
Substrates Batch size
  • 1 6" wafer per run
  • 1 4" wafer per run
  • 1 2" wafer per run
  • Or several smaller pieces on a carrier wafer
. Substrate material allowed
  • Silicon wafers
    • with layers of silicon oxide or silicon (oxy)nitride
  • Quartz wafers
. Possible masking material
  • Photoresist/e-beam resist
  • PolySilicon
  • Silicon oxide or silicon (oxy)nitride
  • Aluminium