Specific Process Knowledge/Lithography/EBeamLithography: Difference between revisions
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As an alternative to PEC, a trilayer reists stack with a thin layer of thermally evaporated Ge can be used [http://avspublications.org/jvst/resource/1/jvstal/v19/i4/p1304_s1]. This reists stack has not yet been tested at DTU Danchip. A process flow for this procedure can be found here [[media:Process_Flow_Trilayer_Ebeam_Resist.docx|Process_Flow_Trilayer_Ebeam_Resist.docx]], but please contact [mailto:Lithography@danchip.dtu.dk Lithography] before use. | As an alternative to PEC, a trilayer reists stack with a thin layer of thermally evaporated Ge can be used [http://avspublications.org/jvst/resource/1/jvstal/v19/i4/p1304_s1]. This reists stack has not yet been tested at DTU Danchip. A process flow for this procedure can be found here [[media:Process_Flow_Trilayer_Ebeam_Resist.docx|Process_Flow_Trilayer_Ebeam_Resist.docx]], but please contact [mailto:Lithography@danchip.dtu.dk Lithography] before use. | ||
= | = Charging of non-conductive substrates = | ||
All substrates are grounded to the cassette when proper loaded. In a non-conducting substrate, the accumulation of charges in the substrates will however destroy the e-beam patterning. To avoid this, a charge dissipating layer is added on top of the e-beam resist; this will provide a conducting layer for the electrons to escape, while high-energy electrons will pass through the layer to expose the resist. | All substrates are grounded to the cassette when proper loaded. In a non-conducting substrate, the accumulation of charges in the substrates will however destroy the e-beam patterning. To avoid this, a charge dissipating layer is added on top of the e-beam resist; this will provide a conducting layer for the electrons to escape, while high-energy electrons will pass through the layer to expose the resist. | ||