Specific Process Knowledge/Etch/IBE⁄IBSD Ionfab 300/IBE Si etch: Difference between revisions

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'''Feedback to this page''': '''[mailto:labadviser@nanolab.dtu.dk?Subject=Feed%20back%20from%20page%20http://labadviser.nanolab.dtu.dk/index.php/Specific_Process_Knowledge/Etch/IBE⁄IBSD_Ionfab_300/IBE_Si_etch  click here]'''
=Results for Si etching in the IBE=
=Results for Si etching in the IBE=
''Made by Kristian Hagsted Rasmussen @ Nanotech in 2011'' <br\>
''Made by Kristian Hagsted Rasmussen. DTU Nanotech in 2011'' <br>


Best recipe with respect to the etch profile and low redeposition:
The silicon etch test was made as a preliminary test of the IBE system, to obtain a feeling of the system capabilities and the different parameters influence on the etch outcome. A throughout characterization of the wafers was not carried out. However, the most important results are listed here.
The table list the best etch definition obtained. The IBE etcher should only be used for silicon etching, if you have a specific need that cannot be accommodated in a RIE tool. This could be excessive amount of metals on the surface or a layer of silicon in a stack of several layers that all must be etched.
The corner definition is strongly dependent on both accelerator and beam voltage and of course the incident angle. However, no interactions between parameters seem to influence the angle outcome. The good corner definition will introduce hare ears at the resist edge. This is best limited by use of thin resist layers slightly thicker than needed to mask for the duration of the etch. Be aware that the selectivity between silicon and resist is poor.
 
 
===Best recipe with respect to the etch profile and low redeposition===
{| border="2" cellspacing="2" cellpadding="3"  
{| border="2" cellspacing="2" cellpadding="3"  
!Parameter
!Parameter
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|'''vvv'''
|'''vvv'''
|-
|-
|Etch rate [nm/min]
|Etch rate in Si [nm/min]
|17-18  
|17-18  
|-
|Etch rate in Silicon nitride (low stress)
|9.1nm/min (2013-05-27 BGHE and Matthias F. Carnoy)
|-
|Etch rate DUV resist
|13.4nm/min (2013-05-27 BGHE and Matthias F. Carnoy)
|-
|}
|}


=Etch results=
 
===Some SEM profile images of the etched stacks===
===Some SEM profile images of the etched stacks===
{| border="1" cellspacing="1" cellpadding="2"  
{| border="1" cellspacing="1" cellpadding="2"  
!
!
[[image:Silicon-IBE-good-b17.jpg|300x300px|thumb|center|Silicon etch in IBE with good corner definition. Small hare ears are obvious at the structure edge.]]
[[image:Silicon-IBE-good-b17.jpg|300x300px|thumb|center|Silicon etch in IBE with good corner definition. Small hare ears are obvious at the structure edge. Substrate etched with Beam current=400mA, Beam voltage=600V, Beam acceleration Voltage=400V, and Stage angle=5°]]
!
!
[[image:Silicon-IBE-bad-b21.jpg|300x300px|thumb|center|Silicon etch in IBE with rounded corners. Large hare ears with ripling are seen at the structure edge.]]
[[image:Silicon-IBE-bad-b21.jpg|300x300px|thumb|center|Silicon etch in IBE with rounded corners. Large hare ears with ripling are seen at the structure edge. Substrate etched with Beam current=500mA, Beam voltage=500V, Beam acceleration Voltage=500V, and Stage angle=10°]]
|}
|}
The silicon etch test was made as a preliminary test of the IBE system, to obtain a felling of the system capabilities and the different parameters influence on the etch outcome. A throughout characterization of the wafers was not carried out. However, the most important results are listed here.
The table list the best etch definition obtained. The IBE etcher should only be used for silicon etching, if you have a specific need that cannot be accommodated in a RIE tool. This could be excessive amount of metals on the surface or a layer of silicon in a stack of several layers that all must be etched.
The corner definition is strongly dependent on both accelerator and beam voltage and of course the incident angle. However, no interactions between parameters seem to influence the angle outcome. The good corner definition will introduce hare ears at the resist edge. This is best limited by use of thin resist layers slightly thicker than needed to mask for the duration of the etch. Be aware that the selectivity between silicon and resist is poor.


===Contour plots of etch rate and corner angle===
===Contour plots of etch rate and corner angle===

Latest revision as of 15:39, 6 February 2023

Feedback to this page: click here


Results for Si etching in the IBE

Made by Kristian Hagsted Rasmussen. DTU Nanotech in 2011

The silicon etch test was made as a preliminary test of the IBE system, to obtain a feeling of the system capabilities and the different parameters influence on the etch outcome. A throughout characterization of the wafers was not carried out. However, the most important results are listed here. The table list the best etch definition obtained. The IBE etcher should only be used for silicon etching, if you have a specific need that cannot be accommodated in a RIE tool. This could be excessive amount of metals on the surface or a layer of silicon in a stack of several layers that all must be etched. The corner definition is strongly dependent on both accelerator and beam voltage and of course the incident angle. However, no interactions between parameters seem to influence the angle outcome. The good corner definition will introduce hare ears at the resist edge. This is best limited by use of thin resist layers slightly thicker than needed to mask for the duration of the etch. Be aware that the selectivity between silicon and resist is poor.


Best recipe with respect to the etch profile and low redeposition

Parameter Best Si etching recipe so fare
Neutalizer current [mA] 450
RF Power [W] 1200
Beam current [mA] 400
Beam voltage [V] 600
Beam accelerator voltage 400
Ar flow to neutralizer [sccm] 6.0
Ar flow to beam [sccm] 6.0
Rotation speed [rpm] 20
Stage angle [degrees] 5
Results vvv
Etch rate in Si [nm/min] 17-18
Etch rate in Silicon nitride (low stress) 9.1nm/min (2013-05-27 BGHE and Matthias F. Carnoy)
Etch rate DUV resist 13.4nm/min (2013-05-27 BGHE and Matthias F. Carnoy)


Some SEM profile images of the etched stacks

Silicon etch in IBE with good corner definition. Small hare ears are obvious at the structure edge. Substrate etched with Beam current=400mA, Beam voltage=600V, Beam acceleration Voltage=400V, and Stage angle=5°
Silicon etch in IBE with rounded corners. Large hare ears with ripling are seen at the structure edge. Substrate etched with Beam current=500mA, Beam voltage=500V, Beam acceleration Voltage=500V, and Stage angle=10°

Contour plots of etch rate and corner angle

IBE etch rate only shows a dependency on Beam Current and Beam Voltage. Values found on the plot should always be tested before use.
The angle in the corner of an etch structure showed a dependency on Beam and Acc. Voltage and Incident angle, with no interactions between any parameters. Values found on the plot should always be tested before use.
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